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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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net: ethernet: realtek: atp: checkpatch errors and warnings corrected
Several warnings and errors of coding style rules corrected. Compile tested. Signed-off-by: Roberto Medina <robertoxmed@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Roberto Medina
David S. Miller
parent
432c856fcf
commit
7aef06db0f
1 changed files with 119 additions and 111 deletions
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@ -6,10 +6,10 @@
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/* The header prepended to received packets. */
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struct rx_header {
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ushort pad; /* Pad. */
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ushort rx_count;
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ushort rx_status; /* Unknown bit assignments :-<. */
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ushort cur_addr; /* Apparently the current buffer address(?) */
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ushort pad; /* Pad. */
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ushort rx_count;
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ushort rx_status; /* Unknown bit assignments :-<. */
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ushort cur_addr; /* Apparently the current buffer address(?) */
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};
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#define PAR_DATA 0
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@ -29,22 +29,25 @@ struct rx_header {
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#define RdAddr 0xC0
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#define HNib 0x10
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enum page0_regs
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{
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/* The first six registers hold the ethernet physical station address. */
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PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5,
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TxCNT0 = 6, TxCNT1 = 7, /* The transmit byte count. */
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TxSTAT = 8, RxSTAT = 9, /* Tx and Rx status. */
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ISR = 10, IMR = 11, /* Interrupt status and mask. */
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CMR1 = 12, /* Command register 1. */
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CMR2 = 13, /* Command register 2. */
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MODSEL = 14, /* Mode select register. */
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MAR = 14, /* Memory address register (?). */
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CMR2_h = 0x1d, };
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enum eepage_regs
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{ PROM_CMD = 6, PROM_DATA = 7 }; /* Note that PROM_CMD is in the "high" bits. */
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enum page0_regs {
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/* The first six registers hold
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* the ethernet physical station address.
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*/
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PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5,
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TxCNT0 = 6, TxCNT1 = 7, /* The transmit byte count. */
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TxSTAT = 8, RxSTAT = 9, /* Tx and Rx status. */
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ISR = 10, IMR = 11, /* Interrupt status and mask. */
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CMR1 = 12, /* Command register 1. */
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CMR2 = 13, /* Command register 2. */
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MODSEL = 14, /* Mode select register. */
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MAR = 14, /* Memory address register (?). */
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CMR2_h = 0x1d,
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};
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enum eepage_regs {
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PROM_CMD = 6,
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PROM_DATA = 7 /* Note that PROM_CMD is in the "high" bits. */
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};
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#define ISR_TxOK 0x01
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#define ISR_RxOK 0x04
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@ -72,141 +75,146 @@ enum eepage_regs
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#define CMR2h_Normal 2 /* Accept physical and broadcast address. */
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#define CMR2h_PROMISC 3 /* Promiscuous mode. */
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/* An inline function used below: it differs from inb() by explicitly return an unsigned
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char, saving a truncation. */
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/* An inline function used below: it differs from inb() by explicitly
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* return an unsigned char, saving a truncation.
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*/
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static inline unsigned char inbyte(unsigned short port)
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{
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unsigned char _v;
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__asm__ __volatile__ ("inb %w1,%b0" :"=a" (_v):"d" (port));
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return _v;
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unsigned char _v;
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__asm__ __volatile__ ("inb %w1,%b0" : "=a" (_v) : "d" (port));
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return _v;
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}
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/* Read register OFFSET.
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This command should always be terminated with read_end(). */
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* This command should always be terminated with read_end().
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*/
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static inline unsigned char read_nibble(short port, unsigned char offset)
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{
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unsigned char retval;
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outb(EOC+offset, port + PAR_DATA);
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outb(RdAddr+offset, port + PAR_DATA);
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inbyte(port + PAR_STATUS); /* Settling time delay */
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retval = inbyte(port + PAR_STATUS);
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outb(EOC+offset, port + PAR_DATA);
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unsigned char retval;
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return retval;
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outb(EOC+offset, port + PAR_DATA);
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outb(RdAddr+offset, port + PAR_DATA);
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inbyte(port + PAR_STATUS); /* Settling time delay */
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retval = inbyte(port + PAR_STATUS);
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outb(EOC+offset, port + PAR_DATA);
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return retval;
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}
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/* Functions for bulk data read. The interrupt line is always disabled. */
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/* Get a byte using read mode 0, reading data from the control lines. */
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static inline unsigned char read_byte_mode0(short ioaddr)
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{
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unsigned char low_nib;
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unsigned char low_nib;
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outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
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inbyte(ioaddr + PAR_STATUS);
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low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
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outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
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inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
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inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
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return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
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outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
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inbyte(ioaddr + PAR_STATUS);
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low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
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outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
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inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
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inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
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return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
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}
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/* The same as read_byte_mode0(), but does multiple inb()s for stability. */
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static inline unsigned char read_byte_mode2(short ioaddr)
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{
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unsigned char low_nib;
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unsigned char low_nib;
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outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
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inbyte(ioaddr + PAR_STATUS);
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low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
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outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
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inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
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return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
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outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
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inbyte(ioaddr + PAR_STATUS);
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low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
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outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
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inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
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return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
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}
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/* Read a byte through the data register. */
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static inline unsigned char read_byte_mode4(short ioaddr)
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{
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unsigned char low_nib;
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unsigned char low_nib;
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outb(RdAddr | MAR, ioaddr + PAR_DATA);
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low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
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outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
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return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
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outb(RdAddr | MAR, ioaddr + PAR_DATA);
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low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
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outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
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return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
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}
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/* Read a byte through the data register, double reading to allow settling. */
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static inline unsigned char read_byte_mode6(short ioaddr)
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{
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unsigned char low_nib;
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unsigned char low_nib;
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outb(RdAddr | MAR, ioaddr + PAR_DATA);
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inbyte(ioaddr + PAR_STATUS);
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low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
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outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
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inbyte(ioaddr + PAR_STATUS);
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return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
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outb(RdAddr | MAR, ioaddr + PAR_DATA);
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inbyte(ioaddr + PAR_STATUS);
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low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
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outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
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inbyte(ioaddr + PAR_STATUS);
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return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
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}
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static inline void
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write_reg(short port, unsigned char reg, unsigned char value)
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{
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unsigned char outval;
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outb(EOC | reg, port + PAR_DATA);
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outval = WrAddr | reg;
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outb(outval, port + PAR_DATA);
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outb(outval, port + PAR_DATA); /* Double write for PS/2. */
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unsigned char outval;
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outval &= 0xf0;
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outval |= value;
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outb(outval, port + PAR_DATA);
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outval &= 0x1f;
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outb(outval, port + PAR_DATA);
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outb(outval, port + PAR_DATA);
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outb(EOC | reg, port + PAR_DATA);
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outval = WrAddr | reg;
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outb(outval, port + PAR_DATA);
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outb(outval, port + PAR_DATA); /* Double write for PS/2. */
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outb(EOC | outval, port + PAR_DATA);
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outval &= 0xf0;
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outval |= value;
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outb(outval, port + PAR_DATA);
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outval &= 0x1f;
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outb(outval, port + PAR_DATA);
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outb(outval, port + PAR_DATA);
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outb(EOC | outval, port + PAR_DATA);
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}
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static inline void
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write_reg_high(short port, unsigned char reg, unsigned char value)
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{
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unsigned char outval = EOC | HNib | reg;
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unsigned char outval = EOC | HNib | reg;
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outb(outval, port + PAR_DATA);
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outval &= WrAddr | HNib | 0x0f;
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outb(outval, port + PAR_DATA);
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outb(outval, port + PAR_DATA); /* Double write for PS/2. */
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outb(outval, port + PAR_DATA);
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outval &= WrAddr | HNib | 0x0f;
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outb(outval, port + PAR_DATA);
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outb(outval, port + PAR_DATA); /* Double write for PS/2. */
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outval = WrAddr | HNib | value;
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outb(outval, port + PAR_DATA);
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outval &= HNib | 0x0f; /* HNib | value */
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outb(outval, port + PAR_DATA);
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outb(outval, port + PAR_DATA);
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outval = WrAddr | HNib | value;
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outb(outval, port + PAR_DATA);
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outval &= HNib | 0x0f; /* HNib | value */
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outb(outval, port + PAR_DATA);
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outb(outval, port + PAR_DATA);
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outb(EOC | HNib | outval, port + PAR_DATA);
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outb(EOC | HNib | outval, port + PAR_DATA);
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}
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/* Write a byte out using nibble mode. The low nibble is written first. */
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static inline void
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write_reg_byte(short port, unsigned char reg, unsigned char value)
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{
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unsigned char outval;
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outb(EOC | reg, port + PAR_DATA); /* Reset the address register. */
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outval = WrAddr | reg;
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outb(outval, port + PAR_DATA);
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outb(outval, port + PAR_DATA); /* Double write for PS/2. */
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unsigned char outval;
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outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA);
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outb(value & 0x0f, port + PAR_DATA);
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value >>= 4;
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outb(value, port + PAR_DATA);
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outb(0x10 | value, port + PAR_DATA);
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outb(0x10 | value, port + PAR_DATA);
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outb(EOC | reg, port + PAR_DATA); /* Reset the address register. */
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outval = WrAddr | reg;
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outb(outval, port + PAR_DATA);
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outb(outval, port + PAR_DATA); /* Double write for PS/2. */
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outb(EOC | value, port + PAR_DATA); /* Reset the address register. */
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outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA);
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outb(value & 0x0f, port + PAR_DATA);
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value >>= 4;
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outb(value, port + PAR_DATA);
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outb(0x10 | value, port + PAR_DATA);
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outb(0x10 | value, port + PAR_DATA);
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outb(EOC | value, port + PAR_DATA); /* Reset the address register. */
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}
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/*
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* Bulk data writes to the packet buffer. The interrupt line remains enabled.
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/* Bulk data writes to the packet buffer. The interrupt line remains enabled.
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* The first, faster method uses only the dataport (data modes 0, 2 & 4).
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* The second (backup) method uses data and control regs (modes 1, 3 & 5).
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* It should only be needed when there is skew between the individual data
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@ -214,28 +222,28 @@ write_reg_byte(short port, unsigned char reg, unsigned char value)
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*/
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static inline void write_byte_mode0(short ioaddr, unsigned char value)
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{
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outb(value & 0x0f, ioaddr + PAR_DATA);
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outb((value>>4) | 0x10, ioaddr + PAR_DATA);
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outb(value & 0x0f, ioaddr + PAR_DATA);
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outb((value>>4) | 0x10, ioaddr + PAR_DATA);
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}
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static inline void write_byte_mode1(short ioaddr, unsigned char value)
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{
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outb(value & 0x0f, ioaddr + PAR_DATA);
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outb(Ctrl_IRQEN | Ctrl_LNibWrite, ioaddr + PAR_CONTROL);
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outb((value>>4) | 0x10, ioaddr + PAR_DATA);
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outb(Ctrl_IRQEN | Ctrl_HNibWrite, ioaddr + PAR_CONTROL);
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outb(value & 0x0f, ioaddr + PAR_DATA);
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outb(Ctrl_IRQEN | Ctrl_LNibWrite, ioaddr + PAR_CONTROL);
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outb((value>>4) | 0x10, ioaddr + PAR_DATA);
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outb(Ctrl_IRQEN | Ctrl_HNibWrite, ioaddr + PAR_CONTROL);
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}
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/* Write 16bit VALUE to the packet buffer: the same as above just doubled. */
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static inline void write_word_mode0(short ioaddr, unsigned short value)
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{
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outb(value & 0x0f, ioaddr + PAR_DATA);
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value >>= 4;
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outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
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value >>= 4;
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outb(value & 0x0f, ioaddr + PAR_DATA);
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value >>= 4;
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outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
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outb(value & 0x0f, ioaddr + PAR_DATA);
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value >>= 4;
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outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
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value >>= 4;
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outb(value & 0x0f, ioaddr + PAR_DATA);
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value >>= 4;
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outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
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}
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/* EEPROM_Ctrl bits. */
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@ -248,10 +256,10 @@ static inline void write_word_mode0(short ioaddr, unsigned short value)
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/* Delay between EEPROM clock transitions. */
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#define eeprom_delay(ticks) \
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do { int _i = 40; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
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do { int _i = 40; while (--_i > 0) { __SLOW_DOWN_IO; } } while (0)
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/* The EEPROM commands include the alway-set leading bit. */
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#define EE_WRITE_CMD(offset) (((5 << 6) + (offset)) << 17)
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#define EE_READ(offset) (((6 << 6) + (offset)) << 17)
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#define EE_READ(offset) (((6 << 6) + (offset)) << 17)
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#define EE_ERASE(offset) (((7 << 6) + (offset)) << 17)
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#define EE_CMD_SIZE 27 /* The command+address+data size. */
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