drm/amd/powerplay: add DFCstate control pptable func for arct

This is the callback function that is going to be invoked
when amdgpu_dpm_set_df_cstate is called to toggle DFCstate

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2020-02-25 19:46:50 +08:00 committed by Alex Deucher
parent 41a468a531
commit 7af8bc5016

View file

@ -127,6 +127,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(WaflTest, PPSMC_MSG_WaflTest),
MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode),
MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable),
MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl),
};
static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
@ -2214,6 +2215,27 @@ static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
}
static int arcturus_set_df_cstate(struct smu_context *smu,
enum pp_df_cstate state)
{
uint32_t smu_version;
int ret;
ret = smu_get_smc_version(smu, NULL, &smu_version);
if (ret) {
pr_err("Failed to get smu version!\n");
return ret;
}
/* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
if (smu_version < 0x360F00) {
pr_err("DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
return -EINVAL;
}
return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state);
}
static const struct pptable_funcs arcturus_ppt_funcs = {
/* translate smu index into arcturus specific index */
.get_smu_msg_index = arcturus_get_smu_msg_index,
@ -2307,6 +2329,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
.get_pptable_power_limit = arcturus_get_pptable_power_limit,
.set_df_cstate = arcturus_set_df_cstate,
};
void arcturus_set_ppt_funcs(struct smu_context *smu)