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drm/i915/display: add intel_crtc_wait_for_next_vblank() and use it
intel_wait_for_vblank() goes through a pipe to crtc lookup, while in most cases we already have the crtc available. Avoid the extra lookups by adding an intel_crtc based helper. v2: - Add intel_crtc_wait_for_next_vblank() helper (Ville) Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/90cfbd8c3e79a742b0ee9e3ae75493acb0785dbb.1638366969.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
c7c90b0b84
commit
7b06894b9b
6 changed files with 32 additions and 27 deletions
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@ -321,8 +321,8 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
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intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
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intel_wait_for_vblank(dev_priv, pipe);
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intel_wait_for_vblank(dev_priv, pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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intel_crtc_wait_for_next_vblank(crtc);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
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intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
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}
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@ -775,7 +775,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
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*/
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if (HAS_GMCH(dev_priv) &&
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intel_set_memory_cxsr(dev_priv, false))
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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/*
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* Gen2 reports pipe underruns whenever all planes are disabled.
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@ -785,7 +785,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
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intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
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intel_plane_disable_arm(plane, crtc_state);
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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}
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unsigned int
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@ -1011,7 +1011,7 @@ bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
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if (cleanup_done)
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continue;
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drm_crtc_wait_one_vblank(crtc);
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intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
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return true;
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}
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@ -1158,7 +1158,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
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}
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/* We need to wait for a vblank before we can disable the plane. */
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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}
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static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
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@ -1389,7 +1389,6 @@ static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
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static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *i915 = to_i915(state->base.dev);
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const struct intel_crtc_state *old_crtc_state =
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intel_atomic_get_old_crtc_state(state, crtc);
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const struct intel_crtc_state *new_crtc_state =
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@ -1415,7 +1414,7 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
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}
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if (need_vbl_wait)
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intel_wait_for_vblank(i915, crtc->pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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}
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static void intel_pre_plane_update(struct intel_atomic_state *state,
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@ -1434,7 +1433,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
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hsw_disable_ips(old_crtc_state);
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if (intel_fbc_pre_update(state, crtc))
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intel_wait_for_vblank(dev_priv, pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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if (!needs_async_flip_vtd_wa(old_crtc_state) &&
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needs_async_flip_vtd_wa(new_crtc_state))
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@ -1466,7 +1465,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
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*/
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if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
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new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
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intel_wait_for_vblank(dev_priv, pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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/*
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* IVB workaround: must disable low power watermarks for at least
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@ -1477,7 +1476,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
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*/
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if (old_crtc_state->hw.active &&
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new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
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intel_wait_for_vblank(dev_priv, pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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/*
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* If we're doing a modeset we don't need to do any
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@ -1893,8 +1892,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
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* in case there are more corner cases we don't know about.
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*/
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if (new_crtc_state->has_pch_encoder) {
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intel_wait_for_vblank(dev_priv, pipe);
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intel_wait_for_vblank(dev_priv, pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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intel_crtc_wait_for_next_vblank(crtc);
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}
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
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intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
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@ -2094,7 +2093,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
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intel_encoders_enable(state, crtc);
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if (psl_clkgate_wa) {
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intel_wait_for_vblank(dev_priv, pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
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}
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@ -2529,7 +2528,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
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/* prevents spurious underruns */
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if (DISPLAY_VER(dev_priv) == 2)
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intel_wait_for_vblank(dev_priv, pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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}
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static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
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@ -2560,7 +2559,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
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* wait for planes to fully turn off before disabling the pipe.
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*/
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if (DISPLAY_VER(dev_priv) == 2)
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intel_wait_for_vblank(dev_priv, pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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intel_encoders_disable(state, crtc);
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@ -4645,7 +4644,8 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
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drm_atomic_state_put(state);
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/* let the connector get through one full cycle before testing */
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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return true;
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fail:
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@ -8462,7 +8462,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
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if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
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&old_crtc_state->wm.skl.ddb) &&
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(update_pipes | modeset_pipes))
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intel_wait_for_vblank(dev_priv, pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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}
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}
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@ -2019,21 +2019,27 @@ intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
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return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
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}
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static inline void
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intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc)
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{
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drm_crtc_wait_one_vblank(&crtc->base);
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}
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static inline void
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intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
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{
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struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
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drm_crtc_wait_one_vblank(&crtc->base);
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intel_crtc_wait_for_next_vblank(crtc);
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}
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static inline void
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intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
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{
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const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
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struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
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if (crtc->active)
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intel_wait_for_vblank(dev_priv, pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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}
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static inline bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
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@ -3905,7 +3905,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
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to_intel_crtc_state(crtc->base.state);
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/* Keep underrun reporting disabled until things are stable */
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
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if (crtc_state->has_pch_encoder)
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@ -1842,7 +1842,7 @@ static void intel_enable_sdvo(struct intel_atomic_state *state,
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intel_sdvo_write_sdvox(intel_sdvo, temp);
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for (i = 0; i < 2; i++)
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
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/*
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@ -924,8 +924,7 @@ intel_enable_tv(struct intel_atomic_state *state,
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struct drm_i915_private *dev_priv = to_i915(dev);
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/* Prevents vblank waits from timing out in intel_tv_detect_type() */
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intel_wait_for_vblank(dev_priv,
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to_intel_crtc(pipe_config->uapi.crtc)->pipe);
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intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc));
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intel_de_write(dev_priv, TV_CTL,
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intel_de_read(dev_priv, TV_CTL) | TV_ENC_ENABLE);
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@ -1618,7 +1617,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
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intel_de_write(dev_priv, TV_DAC, tv_dac);
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intel_de_posting_read(dev_priv, TV_DAC);
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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type = -1;
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tv_dac = intel_de_read(dev_priv, TV_DAC);
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@ -1651,7 +1650,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
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intel_de_posting_read(dev_priv, TV_CTL);
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/* For unknown reasons the hw barfs if we don't do this vblank wait. */
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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intel_crtc_wait_for_next_vblank(crtc);
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/* Restore interrupt config */
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if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
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