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arm64: dts: r8a7795: Add L2 cache-controller nodes

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Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2016-01-16 15:17:36 +01:00 committed by Simon Horman
parent a3fc85e27b
commit 7b337e61a4
1 changed files with 8 additions and 0 deletions
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8
arch/arm64/boot/dts/renesas/r8a7795.dtsi
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@ -39,6 +39,7 @@ a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
next-level-cache = <&L2_CA57>;
enable-method = "psci";
};
@ -46,22 +47,29 @@ a57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x1>;
device_type = "cpu";
next-level-cache = <&L2_CA57>;
enable-method = "psci";
};
a57_2: cpu@2 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x2>;
device_type = "cpu";
next-level-cache = <&L2_CA57>;
enable-method = "psci";
};
a57_3: cpu@3 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x3>;
device_type = "cpu";
next-level-cache = <&L2_CA57>;
enable-method = "psci";
};
};
L2_CA57: cache-controller@0 {
compatible = "cache";
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;