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KVM: PPC: Book3S HV: XIVE: Add a control to sync the sources
This control will be used by the H_INT_SYNC hcall from QEMU to flush event notifications on the XIVE IC owning the source. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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3 changed files with 45 additions and 0 deletions
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@ -92,3 +92,11 @@ the legacy interrupt mode, referred as XICS (POWER7/8).
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-EINVAL: Invalid queue address
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-EINVAL: Invalid queue address
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-EFAULT: Invalid user pointer for attr->addr.
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-EFAULT: Invalid user pointer for attr->addr.
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-EIO: Configuration of the underlying HW failed
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-EIO: Configuration of the underlying HW failed
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5. KVM_DEV_XIVE_GRP_SOURCE_SYNC (write only)
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Synchronize the source to flush event notifications
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Attributes:
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Interrupt source number (64-bit)
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Errors:
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-ENOENT: Unknown source number
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-EINVAL: Not initialized source number
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@ -683,6 +683,7 @@ struct kvm_ppc_cpu_char {
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#define KVM_DEV_XIVE_GRP_SOURCE 2 /* 64-bit source identifier */
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#define KVM_DEV_XIVE_GRP_SOURCE 2 /* 64-bit source identifier */
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#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
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#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
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#define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */
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#define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */
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#define KVM_DEV_XIVE_GRP_SOURCE_SYNC 5 /* 64-bit source identifier */
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/* Layout of 64-bit XIVE source attribute values */
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/* Layout of 64-bit XIVE source attribute values */
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#define KVM_XIVE_LEVEL_SENSITIVE (1ULL << 0)
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#define KVM_XIVE_LEVEL_SENSITIVE (1ULL << 0)
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@ -335,6 +335,38 @@ static int kvmppc_xive_native_set_source_config(struct kvmppc_xive *xive,
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priority, masked, eisn);
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priority, masked, eisn);
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}
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}
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static int kvmppc_xive_native_sync_source(struct kvmppc_xive *xive,
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long irq, u64 addr)
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{
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struct kvmppc_xive_src_block *sb;
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struct kvmppc_xive_irq_state *state;
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struct xive_irq_data *xd;
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u32 hw_num;
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u16 src;
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int rc = 0;
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pr_devel("%s irq=0x%lx", __func__, irq);
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sb = kvmppc_xive_find_source(xive, irq, &src);
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if (!sb)
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return -ENOENT;
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state = &sb->irq_state[src];
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rc = -EINVAL;
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arch_spin_lock(&sb->lock);
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if (state->valid) {
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kvmppc_xive_select_irq(state, &hw_num, &xd);
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xive_native_sync_source(hw_num);
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rc = 0;
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}
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arch_spin_unlock(&sb->lock);
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return rc;
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}
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static int xive_native_validate_queue_size(u32 qshift)
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static int xive_native_validate_queue_size(u32 qshift)
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{
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{
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/*
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/*
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@ -670,6 +702,9 @@ static int kvmppc_xive_native_set_attr(struct kvm_device *dev,
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case KVM_DEV_XIVE_GRP_EQ_CONFIG:
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case KVM_DEV_XIVE_GRP_EQ_CONFIG:
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return kvmppc_xive_native_set_queue_config(xive, attr->attr,
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return kvmppc_xive_native_set_queue_config(xive, attr->attr,
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attr->addr);
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attr->addr);
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case KVM_DEV_XIVE_GRP_SOURCE_SYNC:
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return kvmppc_xive_native_sync_source(xive, attr->attr,
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attr->addr);
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}
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}
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return -ENXIO;
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return -ENXIO;
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}
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}
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@ -699,6 +734,7 @@ static int kvmppc_xive_native_has_attr(struct kvm_device *dev,
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break;
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break;
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case KVM_DEV_XIVE_GRP_SOURCE:
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case KVM_DEV_XIVE_GRP_SOURCE:
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case KVM_DEV_XIVE_GRP_SOURCE_CONFIG:
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case KVM_DEV_XIVE_GRP_SOURCE_CONFIG:
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case KVM_DEV_XIVE_GRP_SOURCE_SYNC:
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if (attr->attr >= KVMPPC_XIVE_FIRST_IRQ &&
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if (attr->attr >= KVMPPC_XIVE_FIRST_IRQ &&
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attr->attr < KVMPPC_XIVE_NR_IRQS)
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attr->attr < KVMPPC_XIVE_NR_IRQS)
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return 0;
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return 0;
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