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habanalabs: type specific MMU cache invalidation
Add the ability to invalidate the necessary MMU cache only. This ability is a prerequisite for future ASICs support. Note that in Goya ASIC, a single cache is used for both host/DRAM mappings and hence this patch should not have any effect on current behavior. Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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7f74d4d335
commit
7b6e4ea0f7
3 changed files with 12 additions and 9 deletions
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@ -2463,7 +2463,8 @@ int goya_mmu_init(struct hl_device *hdev)
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WREG32_AND(mmSTLB_STLB_FEATURE_EN,
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(~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
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hdev->asic_funcs->mmu_invalidate_cache(hdev, true);
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hdev->asic_funcs->mmu_invalidate_cache(hdev, true,
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VM_TYPE_USERPTR | VM_TYPE_PHYS_PACK);
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WREG32(mmMMU_MMU_ENABLE, 1);
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WREG32(mmMMU_SPI_MASK, 0xF);
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@ -4845,7 +4846,8 @@ static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
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goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
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}
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static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard)
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static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
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u32 flags)
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{
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struct goya_device *goya = hdev->asic_specific;
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u32 status, timeout_usec;
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@ -114,8 +114,8 @@ struct hw_queue_properties {
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* @VM_TYPE_PHYS_PACK: mapping of DRAM memory to device virtual address.
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*/
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enum vm_type_t {
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VM_TYPE_USERPTR,
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VM_TYPE_PHYS_PACK
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VM_TYPE_USERPTR = 0x1,
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VM_TYPE_PHYS_PACK = 0x2
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};
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/**
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@ -483,8 +483,8 @@ enum hl_pll_frequency {
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* @get_events_stat: retrieve event queue entries histogram.
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* @read_pte: read MMU page table entry from DRAM.
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* @write_pte: write MMU page table entry to DRAM.
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* @mmu_invalidate_cache: flush MMU STLB cache, either with soft (L1 only) or
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* hard (L0 & L1) flush.
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* @mmu_invalidate_cache: flush MMU STLB host/DRAM cache, either with soft
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* (L1 only) or hard (L0 & L1) flush.
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* @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with
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* ASID-VA-size mask.
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* @send_heartbeat: send is-alive packet to ArmCP and verify response.
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@ -565,7 +565,8 @@ struct hl_asic_funcs {
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u32 *size);
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u64 (*read_pte)(struct hl_device *hdev, u64 addr);
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void (*write_pte)(struct hl_device *hdev, u64 addr, u64 val);
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void (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard);
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void (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard,
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u32 flags);
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void (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard,
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u32 asid, u64 va, u64 size);
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int (*send_heartbeat)(struct hl_device *hdev);
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@ -944,7 +944,7 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args,
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goto map_err;
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}
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hdev->asic_funcs->mmu_invalidate_cache(hdev, false);
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hdev->asic_funcs->mmu_invalidate_cache(hdev, false, *vm_type);
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mutex_unlock(&ctx->mmu_lock);
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@ -1060,7 +1060,7 @@ static int unmap_device_va(struct hl_ctx *ctx, u64 vaddr)
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unmap_phys_pg_pack(ctx, vaddr, phys_pg_pack);
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hdev->asic_funcs->mmu_invalidate_cache(hdev, true);
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hdev->asic_funcs->mmu_invalidate_cache(hdev, true, *vm_type);
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mutex_unlock(&ctx->mmu_lock);
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