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drm/amd/pm: drop unnecessary wrappers around watermark setting
The convertion to "struct dm_pp_clock_range_for_mcif_wm_set_soc15" is totally unnecessary and can be dropped. Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Changfeng Zhu <Changfeng.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
12684c665f
commit
7b9c7e30ab
6 changed files with 78 additions and 206 deletions
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@ -664,49 +664,8 @@ static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
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struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
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wm_with_clock_ranges.wm_dmif_clocks_ranges;
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struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =
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wm_with_clock_ranges.wm_mcif_clocks_ranges;
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int32_t i;
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wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
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wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
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for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
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if (ranges->reader_wm_sets[i].wm_inst > 3)
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wm_dce_clocks[i].wm_set_id = WM_SET_A;
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else
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wm_dce_clocks[i].wm_set_id =
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ranges->reader_wm_sets[i].wm_inst;
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wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
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ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000;
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wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
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ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000;
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wm_dce_clocks[i].wm_max_mem_clk_in_khz =
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ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000;
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wm_dce_clocks[i].wm_min_mem_clk_in_khz =
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ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000;
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}
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for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
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if (ranges->writer_wm_sets[i].wm_inst > 3)
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wm_soc_clocks[i].wm_set_id = WM_SET_A;
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else
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wm_soc_clocks[i].wm_set_id =
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ranges->writer_wm_sets[i].wm_inst;
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wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
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ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000;
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wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
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ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000;
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wm_soc_clocks[i].wm_max_mem_clk_in_khz =
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ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000;
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wm_soc_clocks[i].wm_min_mem_clk_in_khz =
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ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
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}
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smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
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smu_set_watermarks_for_clock_ranges(&adev->smu, ranges);
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return PP_SMU_RESULT_OK;
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}
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@ -917,60 +876,8 @@ static enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct smu_context *smu = &adev->smu;
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struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
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struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
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wm_with_clock_ranges.wm_dmif_clocks_ranges;
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struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =
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wm_with_clock_ranges.wm_mcif_clocks_ranges;
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int32_t i;
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if (!smu->ppt_funcs)
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return PP_SMU_RESULT_UNSUPPORTED;
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wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
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wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
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for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
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if (ranges->reader_wm_sets[i].wm_inst > 3)
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wm_dce_clocks[i].wm_set_id = WM_SET_A;
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else
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wm_dce_clocks[i].wm_set_id =
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ranges->reader_wm_sets[i].wm_inst;
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wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
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ranges->reader_wm_sets[i].min_drain_clk_mhz;
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wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
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ranges->reader_wm_sets[i].max_drain_clk_mhz;
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wm_dce_clocks[i].wm_min_mem_clk_in_khz =
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ranges->reader_wm_sets[i].min_fill_clk_mhz;
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wm_dce_clocks[i].wm_max_mem_clk_in_khz =
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ranges->reader_wm_sets[i].max_fill_clk_mhz;
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}
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for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
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if (ranges->writer_wm_sets[i].wm_inst > 3)
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wm_soc_clocks[i].wm_set_id = WM_SET_A;
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else
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wm_soc_clocks[i].wm_set_id =
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ranges->writer_wm_sets[i].wm_inst;
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wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
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ranges->writer_wm_sets[i].min_fill_clk_mhz;
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wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
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ranges->writer_wm_sets[i].max_fill_clk_mhz;
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wm_soc_clocks[i].wm_min_mem_clk_in_khz =
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ranges->writer_wm_sets[i].min_drain_clk_mhz;
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wm_soc_clocks[i].wm_max_mem_clk_in_khz =
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ranges->writer_wm_sets[i].max_drain_clk_mhz;
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}
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smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
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smu_set_watermarks_for_clock_ranges(&adev->smu, ranges);
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return PP_SMU_RESULT_OK;
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}
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@ -501,7 +501,7 @@ struct pptable_funcs {
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bool (*is_dpm_running)(struct smu_context *smu);
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int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
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int (*set_watermarks_table)(struct smu_context *smu,
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
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struct pp_smu_wm_range_sets *clock_ranges);
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int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
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int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
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int (*set_default_od_settings)(struct smu_context *smu);
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@ -755,7 +755,7 @@ enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
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int smu_write_watermarks_table(struct smu_context *smu);
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int smu_set_watermarks_for_clock_ranges(
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struct smu_context *smu,
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
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struct pp_smu_wm_range_sets *clock_ranges);
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/* smu to display interface */
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extern int smu_display_configuration_change(struct smu_context *smu, const
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@ -1828,7 +1828,7 @@ int smu_write_watermarks_table(struct smu_context *smu)
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}
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int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
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struct pp_smu_wm_range_sets *clock_ranges)
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{
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int ret = 0;
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@ -1589,57 +1589,43 @@ static int navi10_notify_smc_display_config(struct smu_context *smu)
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}
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static int navi10_set_watermarks_table(struct smu_context *smu,
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
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struct pp_smu_wm_range_sets *clock_ranges)
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{
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Watermarks_t *table = smu->smu_table.watermarks_table;
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int ret = 0;
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int i;
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if (clock_ranges) {
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if (clock_ranges->num_wm_dmif_sets > 4 ||
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clock_ranges->num_wm_mcif_sets > 4)
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if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
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clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
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return -EINVAL;
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for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
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table->WatermarkRow[1][i].MinClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
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1000));
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table->WatermarkRow[1][i].MaxClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
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1000));
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table->WatermarkRow[1][i].MinUclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
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1000));
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table->WatermarkRow[1][i].MaxUclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
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1000));
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table->WatermarkRow[1][i].WmSetting = (uint8_t)
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clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
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for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
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table->WatermarkRow[WM_DCEFCLK][i].MinClock =
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clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
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table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
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clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
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table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
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clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
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table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
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clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
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table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
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clock_ranges->reader_wm_sets[i].wm_inst;
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}
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for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
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table->WatermarkRow[0][i].MinClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
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1000));
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table->WatermarkRow[0][i].MaxClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
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1000));
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table->WatermarkRow[0][i].MinUclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
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1000));
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table->WatermarkRow[0][i].MaxUclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
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1000));
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table->WatermarkRow[0][i].WmSetting = (uint8_t)
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clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
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for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
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table->WatermarkRow[WM_SOCCLK][i].MinClock =
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clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
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table->WatermarkRow[WM_SOCCLK][i].MaxClock =
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clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
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table->WatermarkRow[WM_SOCCLK][i].MinUclk =
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clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
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table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
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clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
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table->WatermarkRow[WM_SOCCLK][i].WmSetting =
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clock_ranges->writer_wm_sets[i].wm_inst;
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}
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smu->watermarks_bitmap |= WATERMARKS_EXIST;
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@ -1407,58 +1407,43 @@ static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
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}
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static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
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struct dm_pp_wm_sets_with_clock_ranges_soc15
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*clock_ranges)
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struct pp_smu_wm_range_sets *clock_ranges)
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{
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Watermarks_t *table = smu->smu_table.watermarks_table;
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int ret = 0;
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int i;
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if (clock_ranges) {
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if (clock_ranges->num_wm_dmif_sets > 4 ||
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clock_ranges->num_wm_mcif_sets > 4)
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if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
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clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
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return -EINVAL;
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for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
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table->WatermarkRow[1][i].MinClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
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1000));
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table->WatermarkRow[1][i].MaxClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
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1000));
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table->WatermarkRow[1][i].MinUclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
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1000));
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table->WatermarkRow[1][i].MaxUclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
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1000));
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table->WatermarkRow[1][i].WmSetting = (uint8_t)
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clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
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for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
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table->WatermarkRow[WM_DCEFCLK][i].MinClock =
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clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
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table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
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clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
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table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
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clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
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table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
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clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
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table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
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clock_ranges->reader_wm_sets[i].wm_inst;
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}
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for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
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table->WatermarkRow[0][i].MinClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
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1000));
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table->WatermarkRow[0][i].MaxClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
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1000));
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table->WatermarkRow[0][i].MinUclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
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1000));
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table->WatermarkRow[0][i].MaxUclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
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1000));
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table->WatermarkRow[0][i].WmSetting = (uint8_t)
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clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
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for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
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table->WatermarkRow[WM_SOCCLK][i].MinClock =
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clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
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table->WatermarkRow[WM_SOCCLK][i].MaxClock =
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clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
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table->WatermarkRow[WM_SOCCLK][i].MinUclk =
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clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
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table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
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clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
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table->WatermarkRow[WM_SOCCLK][i].WmSetting =
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clock_ranges->writer_wm_sets[i].wm_inst;
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}
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smu->watermarks_bitmap |= WATERMARKS_EXIST;
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@ -863,50 +863,44 @@ static int renoir_set_performance_level(struct smu_context *smu,
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*/
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static int renoir_set_watermarks_table(
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struct smu_context *smu,
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
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struct pp_smu_wm_range_sets *clock_ranges)
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{
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Watermarks_t *table = smu->smu_table.watermarks_table;
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int ret = 0;
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int i;
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||||
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||||
if (clock_ranges) {
|
||||
if (clock_ranges->num_wm_dmif_sets > 4 ||
|
||||
clock_ranges->num_wm_mcif_sets > 4)
|
||||
if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
|
||||
clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
|
||||
return -EINVAL;
|
||||
|
||||
/* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
|
||||
for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
|
||||
for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
|
||||
table->WatermarkRow[WM_DCFCLK][i].MinClock =
|
||||
cpu_to_le16((uint16_t)
|
||||
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
|
||||
clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
|
||||
table->WatermarkRow[WM_DCFCLK][i].MaxClock =
|
||||
cpu_to_le16((uint16_t)
|
||||
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
|
||||
clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
|
||||
table->WatermarkRow[WM_DCFCLK][i].MinMclk =
|
||||
cpu_to_le16((uint16_t)
|
||||
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
|
||||
clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
|
||||
table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
|
||||
cpu_to_le16((uint16_t)
|
||||
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
|
||||
table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
|
||||
clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
|
||||
clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
|
||||
|
||||
table->WatermarkRow[WM_DCFCLK][i].WmSetting =
|
||||
clock_ranges->reader_wm_sets[i].wm_inst;
|
||||
}
|
||||
|
||||
for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
|
||||
for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
|
||||
table->WatermarkRow[WM_SOCCLK][i].MinClock =
|
||||
cpu_to_le16((uint16_t)
|
||||
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
|
||||
clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
|
||||
table->WatermarkRow[WM_SOCCLK][i].MaxClock =
|
||||
cpu_to_le16((uint16_t)
|
||||
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
|
||||
clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
|
||||
table->WatermarkRow[WM_SOCCLK][i].MinMclk =
|
||||
cpu_to_le16((uint16_t)
|
||||
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
|
||||
clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
|
||||
table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
|
||||
cpu_to_le16((uint16_t)
|
||||
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
|
||||
table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
|
||||
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
|
||||
clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
|
||||
|
||||
table->WatermarkRow[WM_SOCCLK][i].WmSetting =
|
||||
clock_ranges->writer_wm_sets[i].wm_inst;
|
||||
}
|
||||
|
||||
smu->watermarks_bitmap |= WATERMARKS_EXIST;
|
||||
|
|
Loading…
Reference in a new issue