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drm/amdgpu: remove explicit NULL init for parse_cs
sed -i "/\.parse_cs = NULL,/d" drivers/gpu/drm/amd/amdgpu/*.c That's just a leftover from radeon. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e08c90a774
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9 changed files with 0 additions and 12 deletions
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@ -1228,7 +1228,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
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.get_rptr = cik_sdma_ring_get_rptr,
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.get_wptr = cik_sdma_ring_get_wptr,
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.set_wptr = cik_sdma_ring_set_wptr,
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.parse_cs = NULL,
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.emit_ib = cik_sdma_ring_emit_ib,
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.emit_fence = cik_sdma_ring_emit_fence,
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.emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
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@ -3258,7 +3258,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
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.get_rptr = gfx_v6_0_ring_get_rptr,
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.get_wptr = gfx_v6_0_ring_get_wptr,
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.set_wptr = gfx_v6_0_ring_set_wptr_gfx,
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.parse_cs = NULL,
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.emit_ib = gfx_v6_0_ring_emit_ib,
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.emit_fence = gfx_v6_0_ring_emit_fence,
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.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
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@ -3277,7 +3276,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
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.get_rptr = gfx_v6_0_ring_get_rptr,
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.get_wptr = gfx_v6_0_ring_get_wptr,
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.set_wptr = gfx_v6_0_ring_set_wptr_compute,
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.parse_cs = NULL,
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.emit_ib = gfx_v6_0_ring_emit_ib,
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.emit_fence = gfx_v6_0_ring_emit_fence,
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.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
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@ -5147,7 +5147,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
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.get_rptr = gfx_v7_0_ring_get_rptr,
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.get_wptr = gfx_v7_0_ring_get_wptr_gfx,
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.set_wptr = gfx_v7_0_ring_set_wptr_gfx,
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.parse_cs = NULL,
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.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
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.emit_fence = gfx_v7_0_ring_emit_fence_gfx,
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.emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
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@ -5168,7 +5167,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
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.get_rptr = gfx_v7_0_ring_get_rptr,
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.get_wptr = gfx_v7_0_ring_get_wptr_compute,
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.set_wptr = gfx_v7_0_ring_set_wptr_compute,
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.parse_cs = NULL,
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.emit_ib = gfx_v7_0_ring_emit_ib_compute,
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.emit_fence = gfx_v7_0_ring_emit_fence_compute,
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.emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
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@ -6568,7 +6568,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
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.get_rptr = gfx_v8_0_ring_get_rptr,
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.get_wptr = gfx_v8_0_ring_get_wptr_gfx,
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.set_wptr = gfx_v8_0_ring_set_wptr_gfx,
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.parse_cs = NULL,
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.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
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.emit_fence = gfx_v8_0_ring_emit_fence_gfx,
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.emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
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@ -6590,7 +6589,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
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.get_rptr = gfx_v8_0_ring_get_rptr,
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.get_wptr = gfx_v8_0_ring_get_wptr_compute,
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.set_wptr = gfx_v8_0_ring_set_wptr_compute,
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.parse_cs = NULL,
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.emit_ib = gfx_v8_0_ring_emit_ib_compute,
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.emit_fence = gfx_v8_0_ring_emit_fence_compute,
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.emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
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@ -1225,7 +1225,6 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
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.get_rptr = sdma_v2_4_ring_get_rptr,
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.get_wptr = sdma_v2_4_ring_get_wptr,
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.set_wptr = sdma_v2_4_ring_set_wptr,
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.parse_cs = NULL,
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.emit_ib = sdma_v2_4_ring_emit_ib,
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.emit_fence = sdma_v2_4_ring_emit_fence,
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.emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
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@ -1568,7 +1568,6 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
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.get_rptr = sdma_v3_0_ring_get_rptr,
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.get_wptr = sdma_v3_0_ring_get_wptr,
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.set_wptr = sdma_v3_0_ring_set_wptr,
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.parse_cs = NULL,
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.emit_ib = sdma_v3_0_ring_emit_ib,
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.emit_fence = sdma_v3_0_ring_emit_fence,
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.emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
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@ -783,7 +783,6 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
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.get_rptr = si_dma_ring_get_rptr,
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.get_wptr = si_dma_ring_get_wptr,
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.set_wptr = si_dma_ring_set_wptr,
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.parse_cs = NULL,
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.emit_ib = si_dma_ring_emit_ib,
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.emit_fence = si_dma_ring_emit_fence,
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.emit_pipeline_sync = si_dma_ring_emit_pipeline_sync,
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@ -1070,7 +1070,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
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.get_rptr = uvd_v6_0_ring_get_rptr,
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.get_wptr = uvd_v6_0_ring_get_wptr,
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.set_wptr = uvd_v6_0_ring_set_wptr,
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.parse_cs = NULL,
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.emit_ib = uvd_v6_0_ring_emit_ib,
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.emit_fence = uvd_v6_0_ring_emit_fence,
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.emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
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@ -870,7 +870,6 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = {
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.get_rptr = vce_v3_0_ring_get_rptr,
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.get_wptr = vce_v3_0_ring_get_wptr,
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.set_wptr = vce_v3_0_ring_set_wptr,
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.parse_cs = NULL,
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.emit_ib = vce_v3_0_ring_emit_ib,
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.emit_vm_flush = vce_v3_0_emit_vm_flush,
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.emit_pipeline_sync = vce_v3_0_emit_pipeline_sync,
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