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clk: rockchip: add new pll-type for rk3328
The rk3328's pll and clock are similar with rk3036's, it different with pll_mode_mask, the rk3328 soc pll mode only one bit(rk3036 soc have two bits) so these should be independent and separate from the series of rk3328s. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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parent
4d3e84f996
commit
7bed92460d
2 changed files with 14 additions and 3 deletions
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@ -29,6 +29,7 @@
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#define PLL_MODE_SLOW 0x0
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#define PLL_MODE_NORM 0x1
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#define PLL_MODE_DEEP 0x2
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#define PLL_RK3328_MODE_MASK 0x1
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struct rockchip_clk_pll {
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struct clk_hw hw;
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@ -848,7 +849,8 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
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struct clk *pll_clk, *mux_clk;
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char pll_name[20];
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if (num_parents != 2) {
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if ((pll_type != pll_rk3328 && num_parents != 2) ||
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(pll_type == pll_rk3328 && num_parents != 1)) {
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pr_err("%s: needs two parent clocks\n", __func__);
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return ERR_PTR(-EINVAL);
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}
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@ -865,13 +867,17 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
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pll_mux = &pll->pll_mux;
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pll_mux->reg = ctx->reg_base + mode_offset;
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pll_mux->shift = mode_shift;
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pll_mux->mask = PLL_MODE_MASK;
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if (pll_type == pll_rk3328)
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pll_mux->mask = PLL_RK3328_MODE_MASK;
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else
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pll_mux->mask = PLL_MODE_MASK;
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pll_mux->flags = 0;
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pll_mux->lock = &ctx->lock;
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pll_mux->hw.init = &init;
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if (pll_type == pll_rk3036 ||
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pll_type == pll_rk3066 ||
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pll_type == pll_rk3328 ||
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pll_type == pll_rk3399)
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pll_mux->flags |= CLK_MUX_HIWORD_MASK;
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@ -884,7 +890,10 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
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init.flags = CLK_SET_RATE_PARENT;
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init.ops = pll->pll_mux_ops;
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init.parent_names = pll_parents;
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init.num_parents = ARRAY_SIZE(pll_parents);
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if (pll_type == pll_rk3328)
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init.num_parents = 2;
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else
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init.num_parents = ARRAY_SIZE(pll_parents);
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mux_clk = clk_register(NULL, &pll_mux->hw);
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if (IS_ERR(mux_clk))
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@ -918,6 +927,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
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switch (pll_type) {
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case pll_rk3036:
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case pll_rk3328:
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if (!pll->rate_table || IS_ERR(ctx->grf))
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init.ops = &rockchip_rk3036_pll_clk_norate_ops;
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else
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@ -130,6 +130,7 @@ struct clk;
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enum rockchip_pll_type {
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pll_rk3036,
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pll_rk3066,
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pll_rk3328,
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pll_rk3399,
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};
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