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iommu/mediatek: Merge 2 M4U HWs into one iommu domain
In theory, If there are 2 M4U HWs, there should be 2 IOMMU domains. But one IOMMU domain(4GB iova range) is enough for us currently, It's unnecessary to maintain 2 pagetables. Besides, This patch can simplify our consumer code largely. They don't need map a iova range from one domain into another, They can share the iova address easily. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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parent
e6dec92308
commit
7c3a2ec028
2 changed files with 70 additions and 24 deletions
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@ -114,6 +114,27 @@ struct mtk_iommu_domain {
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static struct iommu_ops mtk_iommu_ops;
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static LIST_HEAD(m4ulist); /* List all the M4U HWs */
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#define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list)
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/*
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* There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
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* for the performance.
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*
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* Here always return the mtk_iommu_data of the first probed M4U where the
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* iommu domain information is recorded.
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*/
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static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
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{
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struct mtk_iommu_data *data;
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for_each_m4u(data)
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return data;
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return NULL;
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}
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static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
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{
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return container_of(dom, struct mtk_iommu_domain, domain);
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@ -123,9 +144,12 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
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{
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struct mtk_iommu_data *data = cookie;
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, data->base + REG_MMU_INV_SEL);
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writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
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wmb(); /* Make sure the tlb flush all done */
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for_each_m4u(data) {
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
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data->base + REG_MMU_INV_SEL);
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writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
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wmb(); /* Make sure the tlb flush all done */
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}
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}
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static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size,
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@ -134,12 +158,17 @@ static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size,
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{
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struct mtk_iommu_data *data = cookie;
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, data->base + REG_MMU_INV_SEL);
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for_each_m4u(data) {
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
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data->base + REG_MMU_INV_SEL);
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writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
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writel_relaxed(iova + size - 1, data->base + REG_MMU_INVLD_END_A);
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writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
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data->tlb_flush_active = true;
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writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
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writel_relaxed(iova + size - 1,
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data->base + REG_MMU_INVLD_END_A);
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writel_relaxed(F_MMU_INV_RANGE,
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data->base + REG_MMU_INVALIDATE);
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data->tlb_flush_active = true;
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}
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}
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static void mtk_iommu_tlb_sync(void *cookie)
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@ -148,20 +177,22 @@ static void mtk_iommu_tlb_sync(void *cookie)
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int ret;
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u32 tmp;
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/* Avoid timing out if there's nothing to wait for */
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if (!data->tlb_flush_active)
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return;
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for_each_m4u(data) {
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/* Avoid timing out if there's nothing to wait for */
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if (!data->tlb_flush_active)
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return;
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ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, tmp,
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tmp != 0, 10, 100000);
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if (ret) {
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dev_warn(data->dev,
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"Partial TLB flush timed out, falling back to full flush\n");
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mtk_iommu_tlb_flush_all(cookie);
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ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
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tmp, tmp != 0, 10, 100000);
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if (ret) {
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dev_warn(data->dev,
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"Partial TLB flush timed out, falling back to full flush\n");
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mtk_iommu_tlb_flush_all(cookie);
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}
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/* Clear the CPE status */
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writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
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data->tlb_flush_active = false;
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}
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/* Clear the CPE status */
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writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
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data->tlb_flush_active = false;
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}
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static const struct iommu_gather_ops mtk_iommu_gather_ops = {
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@ -298,10 +329,11 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
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struct device *dev)
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{
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struct mtk_iommu_domain *dom = to_mtk_domain(domain);
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struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
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struct mtk_iommu_data *curdata = dev->iommu_fwspec->iommu_priv;
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struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
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int ret;
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if (!data)
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if (!data || !curdata)
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return -ENODEV;
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if (!data->m4u_dom) {
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@ -313,7 +345,17 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
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}
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}
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mtk_iommu_config(data, dev, true);
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/*
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* Update the pgtable base address register of another M4U HW with the
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* existed pgtable if there are more than one M4U HW.
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*/
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if (!curdata->m4u_dom) {
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curdata->m4u_dom = data->m4u_dom;
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writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
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curdata->base + REG_MMU_PT_BASE_ADDR);
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}
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mtk_iommu_config(curdata, dev, true);
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return 0;
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}
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@ -405,7 +447,7 @@ static void mtk_iommu_remove_device(struct device *dev)
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static struct iommu_group *mtk_iommu_device_group(struct device *dev)
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{
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struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
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struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
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if (!data)
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return ERR_PTR(-ENODEV);
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@ -604,6 +646,8 @@ static int mtk_iommu_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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list_add_tail(&data->list, &m4ulist);
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if (!iommu_present(&platform_bus_type))
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bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
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@ -57,6 +57,8 @@ struct mtk_iommu_data {
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struct iommu_device iommu;
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enum mtk_iommu_plat m4u_plat;
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struct list_head list;
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};
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static inline int compare_of(struct device *dev, void *data)
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