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dmaengine: idxd: Merge definition of dsa_batch_desc into dsa_hw_desc
We don't need a special structure just for batch descriptors. The layout matches the general form for other descriptors. Merge the desc_list_addr field into the union of other aliases for the the third quadword in the structure. Create a union to alias "xfer_size" with "desc_count". Signed-off-by: Tony Luck <tony.luck@intel.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/158387868208.35922.5895104426944263789.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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1 changed files with 5 additions and 16 deletions
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@ -83,21 +83,6 @@ enum dsa_completion_status {
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#define DSA_COMP_STATUS_MASK 0x7f
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#define DSA_COMP_STATUS_WRITE 0x80
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struct dsa_batch_desc {
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uint32_t pasid:20;
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uint32_t rsvd:11;
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uint32_t priv:1;
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uint32_t flags:24;
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uint32_t opcode:8;
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uint64_t completion_addr;
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uint64_t desc_list_addr;
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uint64_t rsvd1;
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uint32_t desc_count;
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uint16_t interrupt_handle;
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uint16_t rsvd2;
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uint8_t rsvd3[24];
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} __attribute__((packed));
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struct dsa_hw_desc {
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uint32_t pasid:20;
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uint32_t rsvd:11;
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@ -109,6 +94,7 @@ struct dsa_hw_desc {
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uint64_t src_addr;
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uint64_t rdback_addr;
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uint64_t pattern;
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uint64_t desc_list_addr;
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};
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union {
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uint64_t dst_addr;
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@ -116,7 +102,10 @@ struct dsa_hw_desc {
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uint64_t src2_addr;
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uint64_t comp_pattern;
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};
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uint32_t xfer_size;
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union {
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uint32_t xfer_size;
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uint32_t desc_count;
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};
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uint16_t int_handle;
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uint16_t rsvd1;
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union {
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