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powerpc/fsl_booke: protect the access to MAS7
The e500v1 doesn't implement the MAS7, so we should avoid to access this register on that implementations. In the current kernel, the access to MAS7 are protected by either CONFIG_PHYS_64BIT or MMU_FTR_BIG_PHYS. Since some code are executed before the code patching, we have to use CONFIG_PHYS_64BIT in these cases. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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d2dc13b533
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2 changed files with 4 additions and 1 deletions
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@ -82,7 +82,9 @@ _ENTRY(_start);
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and r19,r3,r18 /* r19 = page offset */
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and r19,r3,r18 /* r19 = page offset */
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andc r31,r20,r18 /* r31 = page base */
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andc r31,r20,r18 /* r31 = page base */
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or r31,r31,r19 /* r31 = devtree phys addr */
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or r31,r31,r19 /* r31 = devtree phys addr */
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#ifdef CONFIG_PHYS_64BIT
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mfspr r30,SPRN_MAS7
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mfspr r30,SPRN_MAS7
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#endif
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li r25,0 /* phys kernel start (low) */
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li r25,0 /* phys kernel start (low) */
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li r24,0 /* CPU number */
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li r24,0 /* CPU number */
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@ -103,7 +103,8 @@ void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
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if (mmu_has_feature(MMU_FTR_USE_PAIRED_MAS)) {
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if (mmu_has_feature(MMU_FTR_USE_PAIRED_MAS)) {
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mtspr(SPRN_MAS7_MAS3, mas7_3);
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mtspr(SPRN_MAS7_MAS3, mas7_3);
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} else {
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} else {
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mtspr(SPRN_MAS7, upper_32_bits(mas7_3));
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if (mmu_has_feature(MMU_FTR_BIG_PHYS))
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mtspr(SPRN_MAS7, upper_32_bits(mas7_3));
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mtspr(SPRN_MAS3, lower_32_bits(mas7_3));
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mtspr(SPRN_MAS3, lower_32_bits(mas7_3));
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}
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}
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