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drm/omap: fix TILER on OMAP5
On OMAP5 it is not possible to use TILER buffer with CPU when caching or write-combining is used. Doing so leads to errors from the memory manager. However, on OMAP4, write-combining works fine. This patch adds platform specific data for the TILER, and a function tiler_get_cpu_cache_flags() which can be used to get the caching mode to be used. Note that without write-combining the use of the TILER buffer with CPU is unusably slow. It's still good to have it operational for testing purposes. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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2dab0bab6b
commit
7cb0d6c17b
4 changed files with 46 additions and 4 deletions
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@ -153,6 +153,10 @@ struct refill_engine {
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struct list_head idle_node;
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};
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struct dmm_platform_data {
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uint32_t cpu_cache_flags;
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};
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struct dmm {
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struct device *dev;
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void __iomem *base;
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@ -183,6 +187,8 @@ struct dmm {
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/* allocation list and lock */
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struct list_head alloc_head;
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const struct dmm_platform_data *plat_data;
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};
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#endif
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@ -39,6 +39,10 @@
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static struct tcm *containers[TILFMT_NFORMATS];
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static struct dmm *omap_dmm;
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#if defined(CONFIG_OF)
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static const struct of_device_id dmm_of_match[];
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#endif
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/* global spinlock for protecting lists */
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static DEFINE_SPINLOCK(list_lock);
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@ -529,6 +533,11 @@ size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h)
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return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
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}
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uint32_t tiler_get_cpu_cache_flags(void)
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{
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return omap_dmm->plat_data->cpu_cache_flags;
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}
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bool dmm_is_available(void)
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{
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return omap_dmm ? true : false;
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@ -592,6 +601,18 @@ static int omap_dmm_probe(struct platform_device *dev)
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init_waitqueue_head(&omap_dmm->engine_queue);
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if (dev->dev.of_node) {
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const struct of_device_id *match;
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match = of_match_node(dmm_of_match, dev->dev.of_node);
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if (!match) {
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dev_err(&dev->dev, "failed to find matching device node\n");
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return -ENODEV;
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}
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omap_dmm->plat_data = match->data;
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}
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/* lookup hwmod data - base address and irq */
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mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
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if (!mem) {
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@ -972,9 +993,23 @@ static const struct dev_pm_ops omap_dmm_pm_ops = {
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#endif
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#if defined(CONFIG_OF)
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static const struct dmm_platform_data dmm_omap4_platform_data = {
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.cpu_cache_flags = OMAP_BO_WC,
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};
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static const struct dmm_platform_data dmm_omap5_platform_data = {
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.cpu_cache_flags = OMAP_BO_UNCACHED,
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};
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static const struct of_device_id dmm_of_match[] = {
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{ .compatible = "ti,omap4-dmm", },
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{ .compatible = "ti,omap5-dmm", },
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{
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.compatible = "ti,omap4-dmm",
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.data = &dmm_omap4_platform_data,
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},
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{
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.compatible = "ti,omap5-dmm",
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.data = &dmm_omap5_platform_data,
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},
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{},
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};
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#endif
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@ -106,6 +106,7 @@ uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient);
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size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h);
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size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h);
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void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h);
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uint32_t tiler_get_cpu_cache_flags(void);
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bool dmm_is_available(void);
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extern struct platform_driver omap_dmm_driver;
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@ -1359,8 +1359,8 @@ struct drm_gem_object *omap_gem_new(struct drm_device *dev,
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/* currently don't allow cached buffers.. there is some caching
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* stuff that needs to be handled better
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*/
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flags &= ~(OMAP_BO_CACHED|OMAP_BO_UNCACHED);
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flags |= OMAP_BO_WC;
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flags &= ~(OMAP_BO_CACHED|OMAP_BO_WC|OMAP_BO_UNCACHED);
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flags |= tiler_get_cpu_cache_flags();
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/* align dimensions to slot boundaries... */
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tiler_align(gem2fmt(flags),
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