mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-09-14 06:35:12 +00:00
Code Issues Releases Wiki Activity

drm/bridge: anx7625: Tune K value for IVO panel

Browse source 
IVO panel require less input video clock variation than video clock
variation in DP CTS spec.

This patch decreases the K value of ANX7625 which will shrink eDP Tx
video clock variation to meet IVO panel's requirement.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Xin Ji <xji@analogixsemi.com>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20210806104407.2208538-1-xji@analogixsemi.com
This commit is contained in:
Xin Ji 2021-08-06 18:44:07 +08:00 committed by Robert Foss
parent bd03d440e2
commit 7d066dc739
No known key found for this signature in database
GPG key ID: 3EFD900F76D1D784
2 changed files with 24 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

24
drivers/gpu/drm/bridge/analogix/anx7625.c
View file

@ -384,6 +384,25 @@ static int anx7625_odfc_config(struct anx7625_data *ctx,
return ret;
}
/*
* The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz),
* anx7625 defined K ratio for matching MIPI input video clock and
* DP output video clock. Increase K value can match bigger video data
* variation. IVO panel has small variation than DP CTS spec, need
* decrease the K value.
*/
static int anx7625_set_k_value(struct anx7625_data *ctx)
{
struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data;
if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1)
return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_DIGITAL_ADJ_1, 0x3B);
return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_DIGITAL_ADJ_1, 0x3D);
}
static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
{
struct device *dev = &ctx->client->dev;
@ -470,9 +489,8 @@ static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
(n & 0xff));
/* Diff */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_DIGITAL_ADJ_1, 0x3D);
anx7625_set_k_value(ctx);
ret |= anx7625_odfc_config(ctx, post_divider - 1);

4
drivers/gpu/drm/bridge/analogix/anx7625.h
View file

@ -210,7 +210,9 @@
#define MIPI_VIDEO_STABLE_CNT 0x0A
#define MIPI_LANE_CTRL_10 0x0F
#define MIPI_DIGITAL_ADJ_1 0x1B
#define MIPI_DIGITAL_ADJ_1 0x1B
#define IVO_MID0 0x26
#define IVO_MID1 0xCF
#define MIPI_PLL_M_NUM_23_16 0x1E
#define MIPI_PLL_M_NUM_15_8 0x1F