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drm/amd/pp: Switch the tolerable latency for display
Select the lowest MCLK frequency that is within the tolerable latency defined in DISPALY Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3217,7 +3217,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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/* Find the lowest MCLK frequency that is within
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* the tolerable latency defined in DAL
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*/
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latency = 0;
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latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
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for (i = 0; i < data->mclk_latency_table.count; i++) {
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if ((data->mclk_latency_table.entries[i].latency <= latency) &&
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(data->mclk_latency_table.entries[i].frequency >=
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