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drm/i915: Extract ilk_pch_get_config()
Pull the ilk+ PCH state readout into its own function and relocate to the appropriate file. The clock readout parts are perhaps a bit iffy since we depend on the gmch DPLL readout code. But we can think about the clock readout big picture later. Cc: Dave Airlie <airlied@redhat.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211015071625.593-6-ville.syrjala@linux.intel.com Reviewed-by: Dave Airlie <airlied@redhat.com>
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f45d2252ee
commit
7d9ae6332e
4 changed files with 75 additions and 69 deletions
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@ -111,11 +111,6 @@
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#include "skl_universal_plane.h"
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#include "vlv_sideband.h"
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static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config);
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static void ilk_pch_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config);
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static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
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static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
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static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
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@ -4226,50 +4221,9 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
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i9xx_get_pipe_color_config(pipe_config);
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intel_color_get_config(pipe_config);
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if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
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struct intel_shared_dpll *pll;
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enum intel_dpll_id pll_id;
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bool pll_active;
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pipe_config->pixel_multiplier = 1;
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pipe_config->has_pch_encoder = true;
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tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
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pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
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FDI_DP_PORT_WIDTH_SHIFT) + 1;
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ilk_get_fdi_m_n_config(crtc, pipe_config);
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if (HAS_PCH_IBX(dev_priv)) {
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/*
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* The pipe->pch transcoder and pch transcoder->pll
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* mapping is fixed.
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*/
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pll_id = (enum intel_dpll_id) crtc->pipe;
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} else {
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tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
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if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
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pll_id = DPLL_ID_PCH_PLL_B;
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else
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pll_id= DPLL_ID_PCH_PLL_A;
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}
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pipe_config->shared_dpll =
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intel_get_shared_dpll_by_id(dev_priv, pll_id);
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pll = pipe_config->shared_dpll;
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pll_active = intel_dpll_get_hw_state(dev_priv, pll,
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&pipe_config->dpll_hw_state);
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drm_WARN_ON(dev, !pll_active);
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tmp = pipe_config->dpll_hw_state.dpll;
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pipe_config->pixel_multiplier =
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((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
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>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
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ilk_pch_clock_get(crtc, pipe_config);
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} else {
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pipe_config->pixel_multiplier = 1;
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}
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ilk_pch_get_config(pipe_config);
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intel_get_transcoder_timings(crtc, pipe_config);
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intel_get_pipe_src_size(crtc, pipe_config);
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@ -4852,8 +4806,8 @@ static int i9xx_pll_refclk(struct drm_device *dev,
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}
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/* Returns the clock of the currently programmed mode of the given pipe. */
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static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config)
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void i9xx_crtc_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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@ -4963,24 +4917,6 @@ int intel_dotclock_calculate(int link_freq,
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return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
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}
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static void ilk_pch_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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/* read out port_clock from the DPLL */
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i9xx_crtc_clock_get(crtc, pipe_config);
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/*
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* In case there is an active pipe without active ports,
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* we may need some idea for the dotclock anyway.
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* Calculate one based on the FDI configuration.
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*/
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pipe_config->hw.adjusted_mode.crtc_clock =
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intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
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&pipe_config->fdi_m_n);
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}
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/* Returns the currently programmed mode of the given encoder. */
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struct drm_display_mode *
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intel_encoder_current_mode(struct intel_encoder *encoder)
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@ -586,8 +586,9 @@ void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
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enum link_m_n_set m_n);
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void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config);
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void i9xx_crtc_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config);
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int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
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bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
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void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
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void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
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@ -299,6 +299,74 @@ void ilk_pch_enable(struct intel_atomic_state *state,
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ilk_enable_pch_transcoder(crtc_state);
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}
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static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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/* read out port_clock from the DPLL */
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i9xx_crtc_clock_get(crtc, crtc_state);
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/*
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* In case there is an active pipe without active ports,
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* we may need some idea for the dotclock anyway.
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* Calculate one based on the FDI configuration.
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*/
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crtc_state->hw.adjusted_mode.crtc_clock =
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intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state),
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&crtc_state->fdi_m_n);
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}
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void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_shared_dpll *pll;
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enum pipe pipe = crtc->pipe;
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enum intel_dpll_id pll_id;
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bool pll_active;
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u32 tmp;
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if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
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return;
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crtc_state->has_pch_encoder = true;
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tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
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crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
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FDI_DP_PORT_WIDTH_SHIFT) + 1;
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ilk_get_fdi_m_n_config(crtc, crtc_state);
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if (HAS_PCH_IBX(dev_priv)) {
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/*
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* The pipe->pch transcoder and pch transcoder->pll
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* mapping is fixed.
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*/
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pll_id = (enum intel_dpll_id) pipe;
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} else {
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tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
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if (tmp & TRANS_DPLLB_SEL(pipe))
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pll_id = DPLL_ID_PCH_PLL_B;
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else
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pll_id = DPLL_ID_PCH_PLL_A;
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}
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crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
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pll = crtc_state->shared_dpll;
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pll_active = intel_dpll_get_hw_state(dev_priv, pll,
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&crtc_state->dpll_hw_state);
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drm_WARN_ON(&dev_priv->drm, !pll_active);
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tmp = crtc_state->dpll_hw_state.dpll;
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crtc_state->pixel_multiplier =
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((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
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>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
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ilk_pch_clock_get(crtc_state);
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}
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static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
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enum transcoder cpu_transcoder)
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{
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@ -14,6 +14,7 @@ struct intel_crtc_state;
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void ilk_disable_pch_transcoder(struct intel_crtc *crtc);
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void ilk_pch_enable(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void ilk_pch_get_config(struct intel_crtc_state *crtc_state);
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void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
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void lpt_pch_enable(struct intel_atomic_state *state,
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