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wifi: rtw89: support TX diversity for 1T2R chipset
Check RSSI strength to decide which path is better, and then set TX path accordingly. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220908074140.39776-6-pkshih@realtek.com
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6ce472d651
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7dbdf65525
6 changed files with 68 additions and 1 deletions
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@ -2218,6 +2218,7 @@ static void rtw89_track_work(struct work_struct *work)
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rtw89_chip_rfk_track(rtwdev);
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rtw89_phy_ra_update(rtwdev);
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rtw89_phy_cfo_track(rtwdev);
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rtw89_phy_tx_path_div_track(rtwdev);
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if (rtwdev->lps_enabled && !rtwdev->btc.lps)
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rtw89_enter_lps_track(rtwdev);
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@ -34,6 +34,7 @@ extern const struct ieee80211_ops rtw89_ops;
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#define MAX_RSSI 110
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#define RSSI_FACTOR 1
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#define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
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#define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
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#define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
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#define RTW89_HTC_VARIANT_HE 3
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@ -2291,6 +2291,7 @@ static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
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struct ieee80211_rx_status *status = &rtwsta->rx_status;
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struct seq_file *m = (struct seq_file *)data;
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struct rtw89_dev *rtwdev = rtwsta->rtwdev;
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struct rtw89_hal *hal = &rtwdev->hal;
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u8 rssi;
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int i;
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@ -2341,7 +2342,8 @@ static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
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RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi);
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for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
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rssi = ewma_rssi_read(&rtwsta->rssi[i]);
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seq_printf(m, "%d%s", RTW89_RSSI_RAW_TO_DBM(rssi),
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seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi),
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hal->tx_path_diversity && (hal->antenna_tx & BIT(i)) ? "*" : "",
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i + 1 == rtwdev->chip->rf_path_num ? "" : ", ");
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}
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seq_puts(m, "]\n");
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@ -3660,6 +3660,62 @@ void rtw89_phy_dig(struct rtw89_dev *rtwdev)
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rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
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}
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static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta)
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{
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struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
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struct rtw89_dev *rtwdev = rtwsta->rtwdev;
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struct rtw89_vif *rtwvif = rtwsta->rtwvif;
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struct rtw89_hal *hal = &rtwdev->hal;
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bool *done = data;
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u8 rssi_a, rssi_b;
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u32 candidate;
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if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls)
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return;
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if (*done)
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return;
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*done = true;
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rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]);
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rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]);
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if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH)
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candidate = RF_A;
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else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH)
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candidate = RF_B;
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else
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return;
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if (hal->antenna_tx == candidate)
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return;
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hal->antenna_tx = candidate;
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rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta);
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if (hal->antenna_tx == RF_A) {
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rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12);
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rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11);
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} else if (hal->antenna_tx == RF_B) {
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rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11);
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rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12);
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}
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}
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void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev)
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{
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struct rtw89_hal *hal = &rtwdev->hal;
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bool done = false;
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if (!hal->tx_path_diversity)
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return;
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ieee80211_iterate_stations_atomic(rtwdev->hw,
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rtw89_phy_tx_path_div_sta_iter,
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&done);
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}
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static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
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{
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rtw89_phy_ccx_top_setting_init(rtwdev);
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@ -491,6 +491,7 @@ void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
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u32 val);
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void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev);
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void rtw89_phy_dig(struct rtw89_dev *rtwdev);
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void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev);
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void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
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void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
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enum rtw89_mac_idx mac_idx,
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@ -3553,6 +3553,9 @@
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#define B_P0_RXCK_VAL GENMASK(18, 16)
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#define B_P0_TXCK_ON BIT(15)
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#define B_P0_TXCK_VAL GENMASK(14, 12)
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#define R_P0_RFMODE 0x12AC
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#define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
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#define B_P0_RFMODE_MUX GENMASK(11, 4)
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#define R_P0_NRBW 0x12B8
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#define B_P0_NRBW_DBG BIT(30)
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#define R_S0_RXDC 0x12D4
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@ -3659,6 +3662,9 @@
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#define B_P1_EN_SOUND_WO_NDP BIT(1)
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#define R_S1_HW_SI_DIS 0x3200
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#define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
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#define R_P1_RFMODE 0x32AC
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#define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
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#define B_P1_RFMODE_MUX GENMASK(11, 4)
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#define R_P1_DBGMOD 0x32B8
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#define B_P1_DBGMOD_ON BIT(30)
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#define R_S1_RXDC 0x32D4
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