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x86/cpu: Clear SVM feature if disabled by BIOS
When SVM is disabled by BIOS, one cannot use KVM but the SVM feature is still shown in the output of /proc/cpuinfo. On Intel machines, VMX is cleared by init_ia32_feat_ctl(), so do the same on AMD and Hygon processors. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20230921114940.957141-1-pbonzini@redhat.com
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5 changed files with 25 additions and 15 deletions
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@ -1112,12 +1112,16 @@
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#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
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#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
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#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
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/* AMD-V MSRs */
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/* AMD-V MSRs */
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#define MSR_VM_CR 0xc0010114
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#define MSR_VM_IGNNE 0xc0010115
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#define MSR_VM_HSAVE_PA 0xc0010117
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#define SVM_VM_CR_VALID_MASK 0x001fULL
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#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
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#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
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/* Hardware Feedback Interface */
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#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
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#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
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@ -229,10 +229,6 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
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#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
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#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
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#define SVM_VM_CR_VALID_MASK 0x001fULL
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#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
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#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
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#define SVM_NESTED_CTL_NP_ENABLE BIT(0)
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#define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
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#define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
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@ -571,8 +567,6 @@ struct vmcb {
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#define SVM_CPUID_FUNC 0x8000000a
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#define SVM_VM_CR_SVM_DISABLE 4
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#define SVM_SELECTOR_S_SHIFT 4
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#define SVM_SELECTOR_DPL_SHIFT 5
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#define SVM_SELECTOR_P_SHIFT 7
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@ -1031,6 +1031,8 @@ static void zenbleed_check(struct cpuinfo_x86 *c)
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static void init_amd(struct cpuinfo_x86 *c)
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{
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u64 vm_cr;
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early_init_amd(c);
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/*
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@ -1082,6 +1084,14 @@ static void init_amd(struct cpuinfo_x86 *c)
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init_amd_cacheinfo(c);
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if (cpu_has(c, X86_FEATURE_SVM)) {
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rdmsrl(MSR_VM_CR, vm_cr);
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if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) {
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pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n");
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clear_cpu_cap(c, X86_FEATURE_SVM);
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}
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}
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if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) {
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/*
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* Use LFENCE for execution serialization. On families which
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@ -290,6 +290,8 @@ static void early_init_hygon(struct cpuinfo_x86 *c)
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static void init_hygon(struct cpuinfo_x86 *c)
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{
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u64 vm_cr;
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early_init_hygon(c);
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/*
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@ -320,6 +322,14 @@ static void init_hygon(struct cpuinfo_x86 *c)
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init_hygon_cacheinfo(c);
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if (cpu_has(c, X86_FEATURE_SVM)) {
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rdmsrl(MSR_VM_CR, vm_cr);
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if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) {
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pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n");
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clear_cpu_cap(c, X86_FEATURE_SVM);
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}
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}
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if (cpu_has(c, X86_FEATURE_XMM2)) {
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/*
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* Use LFENCE for execution serialization. On families which
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@ -531,8 +531,6 @@ static bool __kvm_is_svm_supported(void)
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int cpu = smp_processor_id();
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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u64 vm_cr;
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if (c->x86_vendor != X86_VENDOR_AMD &&
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c->x86_vendor != X86_VENDOR_HYGON) {
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pr_err("CPU %d isn't AMD or Hygon\n", cpu);
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@ -549,12 +547,6 @@ static bool __kvm_is_svm_supported(void)
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return false;
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}
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rdmsrl(MSR_VM_CR, vm_cr);
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if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) {
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pr_err("SVM disabled (by BIOS) in MSR_VM_CR on CPU %d\n", cpu);
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return false;
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}
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return true;
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}
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