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iio: adc: ti-ads124s08: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: e717f8c6df
("iio: adc: Add the TI ads124s08 ADC code")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-35-jic23@kernel.org
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@ -106,7 +106,7 @@ struct ads124s_private {
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* timestamp is maintained.
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*/
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u32 buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(u32)] __aligned(8);
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u8 data[5] ____cacheline_aligned;
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u8 data[5] __aligned(IIO_DMA_MINALIGN);
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};
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#define ADS124S08_CHAN(index) \
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