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microblaze/PCI: Remove unused PCI BIOS resource allocation
Remove PCI BIOSn unused code which provide's resource allocation for all pci bus and pci host controller memory initialization. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> Link: https://lore.kernel.org/r/20221025065214.4663-8-thippeswamy.havalige@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Thippeswamy Havalige
Michal Simek
parent
4308e3c9e1
commit
7df700afd9
3 changed files with 0 additions and 495 deletions
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@ -74,8 +74,6 @@ struct pci_controller {
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* ranges since the common pci_bus structure can't handle more
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*/
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struct resource io_resource;
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struct resource mem_resources[3];
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int global_number; /* PCI domain number */
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};
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#ifdef CONFIG_PCI
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@ -28,8 +28,6 @@
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#define IOBASE_ISA_IO 3
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#define IOBASE_ISA_MEM 4
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#define pcibios_scan_all_fns(a, b) 0
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/*
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* Set this to 1 if you want the kernel to re-assign all PCI
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* bus numbers (don't do that on ppc64 yet !)
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@ -48,8 +46,6 @@ struct vm_area_struct;
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#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
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#define arch_can_pci_mmap_io() 1
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extern void pcibios_resource_survey(void);
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struct file;
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/* This part of code was originally in xilinx-pci.h */
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@ -44,8 +44,6 @@ resource_size_t isa_mem_base;
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unsigned long isa_io_base;
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EXPORT_SYMBOL(isa_io_base);
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static int pci_bus_count;
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static resource_size_t pcibios_io_size(const struct pci_controller *hose)
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{
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return resource_size(&hose->io_resource);
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@ -93,11 +91,6 @@ unsigned long pci_address_to_pio(phys_addr_t address)
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}
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EXPORT_SYMBOL_GPL(pci_address_to_pio);
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void pcibios_set_master(struct pci_dev *dev)
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{
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/* No special bus mastering setup handling */
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}
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/*
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* Platform support for /proc/bus/pci/X/Y mmap()s.
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*/
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@ -117,494 +110,12 @@ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
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return 0;
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}
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void pci_resource_to_user(const struct pci_dev *dev, int bar,
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const struct resource *rsrc,
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resource_size_t *start, resource_size_t *end)
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{
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struct pci_bus_region region;
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if (rsrc->flags & IORESOURCE_IO) {
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pcibios_resource_to_bus(dev->bus, ®ion,
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(struct resource *) rsrc);
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*start = region.start;
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*end = region.end;
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return;
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}
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/* We pass a CPU physical address to userland for MMIO instead of a
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* BAR value because X is lame and expects to be able to use that
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* to pass to /dev/mem!
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*
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* That means we may have 64-bit values where some apps only expect
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* 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
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*/
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*start = rsrc->start;
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*end = rsrc->end;
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}
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/* Display the domain number in /proc */
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int pci_proc_domain(struct pci_bus *bus)
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{
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return pci_domain_nr(bus);
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}
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/* This header fixup will do the resource fixup for all devices as they are
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* probed, but not for bridge ranges
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*/
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static void pcibios_fixup_resources(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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int i;
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if (!hose) {
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pr_err("No host bridge for PCI dev %s !\n",
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pci_name(dev));
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return;
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}
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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struct resource *res = dev->resource + i;
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if (!res->flags)
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continue;
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if (res->start == 0) {
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pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
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pci_name(dev), i,
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(unsigned long long)res->start,
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(unsigned long long)res->end,
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(unsigned int)res->flags);
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pr_debug("is unassigned\n");
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res->end -= res->start;
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res->start = 0;
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res->flags |= IORESOURCE_UNSET;
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continue;
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}
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pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
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pci_name(dev), i,
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(unsigned long long)res->start,
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(unsigned long long)res->end,
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(unsigned int)res->flags);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
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int pcibios_device_add(struct pci_dev *dev)
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{
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dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
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return 0;
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}
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/*
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* Reparent resource children of pr that conflict with res
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* under res, and make res replace those children.
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*/
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static int __init reparent_resources(struct resource *parent,
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struct resource *res)
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{
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struct resource *p, **pp;
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struct resource **firstpp = NULL;
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for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
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if (p->end < res->start)
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continue;
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if (res->end < p->start)
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break;
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if (p->start < res->start || p->end > res->end)
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return -1; /* not completely contained */
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if (firstpp == NULL)
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firstpp = pp;
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}
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if (firstpp == NULL)
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return -1; /* didn't find any conflicting entries? */
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res->parent = parent;
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res->child = *firstpp;
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res->sibling = *pp;
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*firstpp = res;
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*pp = NULL;
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for (p = res->child; p != NULL; p = p->sibling) {
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p->parent = res;
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pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
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p->name,
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(unsigned long long)p->start,
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(unsigned long long)p->end, res->name);
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}
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return 0;
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}
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/*
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* Handle resources of PCI devices. If the world were perfect, we could
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* just allocate all the resource regions and do nothing more. It isn't.
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* On the other hand, we cannot just re-allocate all devices, as it would
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* require us to know lots of host bridge internals. So we attempt to
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* keep as much of the original configuration as possible, but tweak it
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* when it's found to be wrong.
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*
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* Known BIOS problems we have to work around:
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* - I/O or memory regions not configured
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* - regions configured, but not enabled in the command register
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* - bogus I/O addresses above 64K used
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* - expansion ROMs left enabled (this may sound harmless, but given
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* the fact the PCI specs explicitly allow address decoders to be
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* shared between expansion ROMs and other resource regions, it's
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* at least dangerous)
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*
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* Our solution:
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* (1) Allocate resources for all buses behind PCI-to-PCI bridges.
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* This gives us fixed barriers on where we can allocate.
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* (2) Allocate resources for all enabled devices. If there is
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* a collision, just mark the resource as unallocated. Also
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* disable expansion ROMs during this step.
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* (3) Try to allocate resources for disabled devices. If the
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* resources were assigned correctly, everything goes well,
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* if they weren't, they won't disturb allocation of other
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* resources.
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* (4) Assign new addresses to resources which were either
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* not configured at all or misconfigured. If explicitly
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* requested by the user, configure expansion ROM address
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* as well.
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*/
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static void pcibios_allocate_bus_resources(struct pci_bus *bus)
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{
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struct pci_bus *b;
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int i;
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struct resource *res, *pr;
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pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
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pci_domain_nr(bus), bus->number);
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pci_bus_for_each_resource(bus, res, i) {
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if (!res || !res->flags
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|| res->start > res->end || res->parent)
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continue;
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if (bus->parent == NULL)
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pr = (res->flags & IORESOURCE_IO) ?
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&ioport_resource : &iomem_resource;
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else {
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/* Don't bother with non-root busses when
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* re-assigning all resources. We clear the
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* resource flags as if they were colliding
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* and as such ensure proper re-allocation
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* later.
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*/
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pr = pci_find_parent_resource(bus->self, res);
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if (pr == res) {
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/* this happens when the generic PCI
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* code (wrongly) decides that this
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* bridge is transparent -- paulus
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*/
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continue;
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}
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}
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pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
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bus->self ? pci_name(bus->self) : "PHB",
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bus->number, i,
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(unsigned long long)res->start,
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(unsigned long long)res->end);
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pr_debug("[0x%x], parent %p (%s)\n",
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(unsigned int)res->flags,
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pr, (pr && pr->name) ? pr->name : "nil");
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if (pr && !(pr->flags & IORESOURCE_UNSET)) {
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struct pci_dev *dev = bus->self;
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if (request_resource(pr, res) == 0)
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continue;
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/*
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* Must be a conflict with an existing entry.
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* Move that entry (or entries) under the
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* bridge resource and try again.
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*/
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if (reparent_resources(pr, res) == 0)
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continue;
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if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
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pci_claim_bridge_resource(dev,
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i + PCI_BRIDGE_RESOURCES) == 0)
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continue;
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}
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pr_warn("PCI: Cannot allocate resource region ");
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pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
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res->start = res->end = 0;
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res->flags = 0;
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}
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list_for_each_entry(b, &bus->children, node)
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pcibios_allocate_bus_resources(b);
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}
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static inline void alloc_resource(struct pci_dev *dev, int idx)
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{
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struct resource *pr, *r = &dev->resource[idx];
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pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
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pci_name(dev), idx,
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(unsigned long long)r->start,
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(unsigned long long)r->end,
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(unsigned int)r->flags);
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pr = pci_find_parent_resource(dev, r);
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if (!pr || (pr->flags & IORESOURCE_UNSET) ||
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request_resource(pr, r) < 0) {
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pr_warn("PCI: Cannot allocate resource region %d ", idx);
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pr_cont("of device %s, will remap\n", pci_name(dev));
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if (pr)
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pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
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pr,
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(unsigned long long)pr->start,
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(unsigned long long)pr->end,
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(unsigned int)pr->flags);
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/* We'll assign a new address later */
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r->flags |= IORESOURCE_UNSET;
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r->end -= r->start;
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r->start = 0;
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}
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}
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static void __init pcibios_allocate_resources(int pass)
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{
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struct pci_dev *dev = NULL;
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int idx, disabled;
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u16 command;
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struct resource *r;
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for_each_pci_dev(dev) {
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pci_read_config_word(dev, PCI_COMMAND, &command);
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for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
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r = &dev->resource[idx];
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if (r->parent) /* Already allocated */
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continue;
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if (!r->flags || (r->flags & IORESOURCE_UNSET))
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continue; /* Not assigned at all */
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/* We only allocate ROMs on pass 1 just in case they
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* have been screwed up by firmware
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*/
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if (idx == PCI_ROM_RESOURCE)
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disabled = 1;
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if (r->flags & IORESOURCE_IO)
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disabled = !(command & PCI_COMMAND_IO);
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else
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disabled = !(command & PCI_COMMAND_MEMORY);
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if (pass == disabled)
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alloc_resource(dev, idx);
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}
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if (pass)
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continue;
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r = &dev->resource[PCI_ROM_RESOURCE];
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if (r->flags) {
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/* Turn the ROM off, leave the resource region,
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* but keep it unregistered.
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*/
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u32 reg;
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pci_read_config_dword(dev, dev->rom_base_reg, ®);
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if (reg & PCI_ROM_ADDRESS_ENABLE) {
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pr_debug("PCI: Switching off ROM of %s\n",
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pci_name(dev));
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r->flags &= ~IORESOURCE_ROM_ENABLE;
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pci_write_config_dword(dev, dev->rom_base_reg,
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reg & ~PCI_ROM_ADDRESS_ENABLE);
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}
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}
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}
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}
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static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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resource_size_t offset;
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struct resource *res, *pres;
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int i;
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pr_debug("Reserving legacy ranges for domain %04x\n",
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pci_domain_nr(bus));
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/* Check for IO */
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if (!(hose->io_resource.flags & IORESOURCE_IO))
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goto no_io;
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offset = (unsigned long)hose->io_base_virt - _IO_BASE;
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res = kzalloc(sizeof(struct resource), GFP_KERNEL);
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BUG_ON(res == NULL);
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res->name = "Legacy IO";
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res->flags = IORESOURCE_IO;
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res->start = offset;
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res->end = (offset + 0xfff) & 0xfffffffful;
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pr_debug("Candidate legacy IO: %pR\n", res);
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if (request_resource(&hose->io_resource, res)) {
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pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
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pci_domain_nr(bus), bus->number, res);
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kfree(res);
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}
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no_io:
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/* Check for memory */
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offset = hose->pci_mem_offset;
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pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
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for (i = 0; i < 3; i++) {
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pres = &hose->mem_resources[i];
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if (!(pres->flags & IORESOURCE_MEM))
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continue;
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pr_debug("hose mem res: %pR\n", pres);
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if ((pres->start - offset) <= 0xa0000 &&
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(pres->end - offset) >= 0xbffff)
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break;
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}
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if (i >= 3)
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return;
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res = kzalloc(sizeof(struct resource), GFP_KERNEL);
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BUG_ON(res == NULL);
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res->name = "Legacy VGA memory";
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res->flags = IORESOURCE_MEM;
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res->start = 0xa0000 + offset;
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res->end = 0xbffff + offset;
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pr_debug("Candidate VGA memory: %pR\n", res);
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if (request_resource(pres, res)) {
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pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
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pci_domain_nr(bus), bus->number, res);
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kfree(res);
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}
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}
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void __init pcibios_resource_survey(void)
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{
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struct pci_bus *b;
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/* Allocate and assign resources. If we re-assign everything, then
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* we skip the allocate phase
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*/
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list_for_each_entry(b, &pci_root_buses, node)
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pcibios_allocate_bus_resources(b);
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pcibios_allocate_resources(0);
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pcibios_allocate_resources(1);
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/* Before we start assigning unassigned resource, we try to reserve
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* the low IO area and the VGA memory area if they intersect the
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* bus available resources to avoid allocating things on top of them
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*/
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list_for_each_entry(b, &pci_root_buses, node)
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pcibios_reserve_legacy_regions(b);
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/* Now proceed to assigning things that were left unassigned */
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pr_debug("PCI: Assigning unassigned resources...\n");
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pci_assign_unassigned_resources();
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}
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static void pcibios_setup_phb_resources(struct pci_controller *hose,
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struct list_head *resources)
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{
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unsigned long io_offset;
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struct resource *res;
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int i;
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/* Hookup PHB IO resource */
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res = &hose->io_resource;
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/* Fixup IO space offset */
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io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
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res->start = (res->start + io_offset) & 0xffffffffu;
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res->end = (res->end + io_offset) & 0xffffffffu;
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if (!res->flags) {
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pr_warn("PCI: I/O resource not set for host ");
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pr_cont("bridge %pOF (domain %d)\n",
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hose->dn, hose->global_number);
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/* Workaround for lack of IO resource only on 32-bit */
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res->start = (unsigned long)hose->io_base_virt - isa_io_base;
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res->end = res->start + IO_SPACE_LIMIT;
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res->flags = IORESOURCE_IO;
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}
|
||||
pci_add_resource_offset(resources, res,
|
||||
(__force resource_size_t)(hose->io_base_virt - _IO_BASE));
|
||||
|
||||
pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
|
||||
(unsigned long long)res->start,
|
||||
(unsigned long long)res->end,
|
||||
(unsigned long)res->flags);
|
||||
|
||||
/* Hookup PHB Memory resources */
|
||||
for (i = 0; i < 3; ++i) {
|
||||
res = &hose->mem_resources[i];
|
||||
if (!res->flags) {
|
||||
if (i > 0)
|
||||
continue;
|
||||
pr_err("PCI: Memory resource 0 not set for ");
|
||||
pr_cont("host bridge %pOF (domain %d)\n",
|
||||
hose->dn, hose->global_number);
|
||||
|
||||
/* Workaround for lack of MEM resource only on 32-bit */
|
||||
res->start = hose->pci_mem_offset;
|
||||
res->end = (resource_size_t)-1LL;
|
||||
res->flags = IORESOURCE_MEM;
|
||||
|
||||
}
|
||||
pci_add_resource_offset(resources, res, hose->pci_mem_offset);
|
||||
|
||||
pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
|
||||
i, (unsigned long long)res->start,
|
||||
(unsigned long long)res->end,
|
||||
(unsigned long)res->flags);
|
||||
}
|
||||
|
||||
pr_debug("PCI: PHB MEM offset = %016llx\n",
|
||||
(unsigned long long)hose->pci_mem_offset);
|
||||
pr_debug("PCI: PHB IO offset = %08lx\n",
|
||||
(unsigned long)hose->io_base_virt - _IO_BASE);
|
||||
}
|
||||
|
||||
static void pcibios_scan_phb(struct pci_controller *hose)
|
||||
{
|
||||
LIST_HEAD(resources);
|
||||
struct pci_bus *bus;
|
||||
struct device_node *node = hose->dn;
|
||||
|
||||
pr_debug("PCI: Scanning PHB %pOF\n", node);
|
||||
|
||||
pcibios_setup_phb_resources(hose, &resources);
|
||||
|
||||
bus = pci_scan_root_bus(hose->parent, hose->first_busno,
|
||||
hose->ops, hose, &resources);
|
||||
if (bus == NULL) {
|
||||
pr_err("Failed to create bus for PCI domain %04x\n",
|
||||
hose->global_number);
|
||||
pci_free_resource_list(&resources);
|
||||
return;
|
||||
}
|
||||
bus->busn_res.start = hose->first_busno;
|
||||
hose->bus = bus;
|
||||
|
||||
hose->last_busno = bus->busn_res.end;
|
||||
}
|
||||
|
||||
static int __init pcibios_init(void)
|
||||
{
|
||||
struct pci_controller *hose, *tmp;
|
||||
int next_busno = 0;
|
||||
|
||||
pr_info("PCI: Probing PCI hardware\n");
|
||||
|
||||
/* Scan all of the recorded PCI controllers. */
|
||||
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
|
||||
hose->last_busno = 0xff;
|
||||
pcibios_scan_phb(hose);
|
||||
if (next_busno <= hose->last_busno)
|
||||
next_busno = hose->last_busno + 1;
|
||||
}
|
||||
pci_bus_count = next_busno;
|
||||
|
||||
/* Call common code to handle resource allocation */
|
||||
pcibios_resource_survey();
|
||||
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
|
||||
if (hose->bus)
|
||||
pci_bus_add_devices(hose->bus);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(pcibios_init);
|
||||
|
||||
static struct pci_controller *pci_bus_to_hose(int bus)
|
||||
{
|
||||
struct pci_controller *hose, *tmp;
|
||||
|
|
|
|||
Loading…
Reference in a new issue