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drm/amdgpu: clean up pageflip interrupt handling 

Check to make sure we aren't touching a non-existent
display controller and simplify the code.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2015-10-09 11:38:49 -04:00
parent c113ea1c4f
commit 7dfac8965f
3 changed files with 51 additions and 159 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

70
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
View File

@ -3305,37 +3305,20 @@ static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
unsigned type,
enum amdgpu_interrupt_state state)
{
u32 reg, reg_block;
/* now deal with page flip IRQ */
switch (type) {
case AMDGPU_PAGEFLIP_IRQ_D1:
reg_block = CRTC0_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D2:
reg_block = CRTC1_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D3:
reg_block = CRTC2_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D4:
reg_block = CRTC3_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D5:
reg_block = CRTC4_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D6:
reg_block = CRTC5_REGISTER_OFFSET;
break;
default:
DRM_ERROR("invalid pageflip crtc %d\n", type);
return -EINVAL;
u32 reg;
if (type >= adev->mode_info.num_crtc) {
DRM_ERROR("invalid pageflip crtc %d\n", type);
return -EINVAL;
}
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
if (state == AMDGPU_IRQ_STATE_DISABLE)
WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
else
WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
return 0;
}
@ -3344,7 +3327,6 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
int reg_block;
unsigned long flags;
unsigned crtc_id;
struct amdgpu_crtc *amdgpu_crtc;
@ -3353,33 +3335,15 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
crtc_id = (entry->src_id - 8) >> 1;
amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
/* ack the interrupt */
switch(crtc_id){
case AMDGPU_PAGEFLIP_IRQ_D1:
reg_block = CRTC0_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D2:
reg_block = CRTC1_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D3:
reg_block = CRTC2_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D4:
reg_block = CRTC3_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D5:
reg_block = CRTC4_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D6:
reg_block = CRTC5_REGISTER_OFFSET;
break;
default:
DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
return -EINVAL;
if (crtc_id >= adev->mode_info.num_crtc) {
DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
return -EINVAL;
}
if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
/* IRQ could occur when in initial stage */
if (amdgpu_crtc == NULL)

70
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
View File

@ -3281,37 +3281,20 @@ static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
unsigned type,
enum amdgpu_interrupt_state state)
{
u32 reg, reg_block;
/* now deal with page flip IRQ */
switch (type) {
case AMDGPU_PAGEFLIP_IRQ_D1:
reg_block = CRTC0_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D2:
reg_block = CRTC1_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D3:
reg_block = CRTC2_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D4:
reg_block = CRTC3_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D5:
reg_block = CRTC4_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D6:
reg_block = CRTC5_REGISTER_OFFSET;
break;
default:
DRM_ERROR("invalid pageflip crtc %d\n", type);
return -EINVAL;
u32 reg;
if (type >= adev->mode_info.num_crtc) {
DRM_ERROR("invalid pageflip crtc %d\n", type);
return -EINVAL;
}
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
if (state == AMDGPU_IRQ_STATE_DISABLE)
WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
else
WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
return 0;
}
@ -3320,7 +3303,6 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
int reg_block;
unsigned long flags;
unsigned crtc_id;
struct amdgpu_crtc *amdgpu_crtc;
@ -3329,33 +3311,15 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
crtc_id = (entry->src_id - 8) >> 1;
amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
/* ack the interrupt */
switch(crtc_id){
case AMDGPU_PAGEFLIP_IRQ_D1:
reg_block = CRTC0_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D2:
reg_block = CRTC1_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D3:
reg_block = CRTC2_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D4:
reg_block = CRTC3_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D5:
reg_block = CRTC4_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D6:
reg_block = CRTC5_REGISTER_OFFSET;
break;
default:
DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
return -EINVAL;
if (crtc_id >= adev->mode_info.num_crtc) {
DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
return -EINVAL;
}
if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
/* IRQ could occur when in initial stage */
if(amdgpu_crtc == NULL)

70
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
View File

@ -3312,37 +3312,20 @@ static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
unsigned type,
enum amdgpu_interrupt_state state)
{
u32 reg, reg_block;
/* now deal with page flip IRQ */
switch (type) {
case AMDGPU_PAGEFLIP_IRQ_D1:
reg_block = CRTC0_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D2:
reg_block = CRTC1_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D3:
reg_block = CRTC2_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D4:
reg_block = CRTC3_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D5:
reg_block = CRTC4_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D6:
reg_block = CRTC5_REGISTER_OFFSET;
break;
default:
DRM_ERROR("invalid pageflip crtc %d\n", type);
return -EINVAL;
u32 reg;
if (type >= adev->mode_info.num_crtc) {
DRM_ERROR("invalid pageflip crtc %d\n", type);
return -EINVAL;
}
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
if (state == AMDGPU_IRQ_STATE_DISABLE)
WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
else
WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
return 0;
}
@ -3351,7 +3334,6 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
int reg_block;
unsigned long flags;
unsigned crtc_id;
struct amdgpu_crtc *amdgpu_crtc;
@ -3360,33 +3342,15 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
crtc_id = (entry->src_id - 8) >> 1;
amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
/* ack the interrupt */
switch(crtc_id){
case AMDGPU_PAGEFLIP_IRQ_D1:
reg_block = CRTC0_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D2:
reg_block = CRTC1_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D3:
reg_block = CRTC2_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D4:
reg_block = CRTC3_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D5:
reg_block = CRTC4_REGISTER_OFFSET;
break;
case AMDGPU_PAGEFLIP_IRQ_D6:
reg_block = CRTC5_REGISTER_OFFSET;
break;
default:
DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
return -EINVAL;
if (crtc_id >= adev->mode_info.num_crtc) {
DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
return -EINVAL;
}
if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
/* IRQ could occur when in initial stage */
if (amdgpu_crtc == NULL)