mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-06 00:39:48 +00:00
drm/amdgpu: clean up pageflip interrupt handling
Check to make sure we aren't touching a non-existent display controller and simplify the code. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
c113ea1c4f
commit
7dfac8965f
3 changed files with 51 additions and 159 deletions
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@ -3305,37 +3305,20 @@ static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
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unsigned type,
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unsigned type,
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enum amdgpu_interrupt_state state)
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enum amdgpu_interrupt_state state)
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{
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{
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u32 reg, reg_block;
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u32 reg;
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/* now deal with page flip IRQ */
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switch (type) {
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if (type >= adev->mode_info.num_crtc) {
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case AMDGPU_PAGEFLIP_IRQ_D1:
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DRM_ERROR("invalid pageflip crtc %d\n", type);
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reg_block = CRTC0_REGISTER_OFFSET;
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return -EINVAL;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D2:
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reg_block = CRTC1_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D3:
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reg_block = CRTC2_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D4:
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reg_block = CRTC3_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D5:
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reg_block = CRTC4_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D6:
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reg_block = CRTC5_REGISTER_OFFSET;
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break;
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default:
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DRM_ERROR("invalid pageflip crtc %d\n", type);
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return -EINVAL;
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}
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}
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reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
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reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
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if (state == AMDGPU_IRQ_STATE_DISABLE)
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if (state == AMDGPU_IRQ_STATE_DISABLE)
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WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
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reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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else
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else
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WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
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reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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return 0;
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return 0;
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}
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}
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@ -3344,7 +3327,6 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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struct amdgpu_iv_entry *entry)
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{
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{
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int reg_block;
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unsigned long flags;
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unsigned long flags;
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unsigned crtc_id;
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unsigned crtc_id;
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struct amdgpu_crtc *amdgpu_crtc;
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struct amdgpu_crtc *amdgpu_crtc;
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@ -3353,33 +3335,15 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
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crtc_id = (entry->src_id - 8) >> 1;
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crtc_id = (entry->src_id - 8) >> 1;
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amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
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amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
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/* ack the interrupt */
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if (crtc_id >= adev->mode_info.num_crtc) {
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switch(crtc_id){
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DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
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case AMDGPU_PAGEFLIP_IRQ_D1:
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return -EINVAL;
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reg_block = CRTC0_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D2:
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reg_block = CRTC1_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D3:
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reg_block = CRTC2_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D4:
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reg_block = CRTC3_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D5:
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reg_block = CRTC4_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D6:
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reg_block = CRTC5_REGISTER_OFFSET;
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break;
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default:
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DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
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return -EINVAL;
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}
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}
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if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
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if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
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WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
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GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
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WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
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GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
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/* IRQ could occur when in initial stage */
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/* IRQ could occur when in initial stage */
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if (amdgpu_crtc == NULL)
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if (amdgpu_crtc == NULL)
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@ -3281,37 +3281,20 @@ static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
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unsigned type,
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unsigned type,
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enum amdgpu_interrupt_state state)
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enum amdgpu_interrupt_state state)
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{
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{
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u32 reg, reg_block;
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u32 reg;
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/* now deal with page flip IRQ */
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switch (type) {
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if (type >= adev->mode_info.num_crtc) {
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case AMDGPU_PAGEFLIP_IRQ_D1:
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DRM_ERROR("invalid pageflip crtc %d\n", type);
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reg_block = CRTC0_REGISTER_OFFSET;
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return -EINVAL;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D2:
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reg_block = CRTC1_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D3:
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reg_block = CRTC2_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D4:
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reg_block = CRTC3_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D5:
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reg_block = CRTC4_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D6:
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reg_block = CRTC5_REGISTER_OFFSET;
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break;
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default:
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DRM_ERROR("invalid pageflip crtc %d\n", type);
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return -EINVAL;
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}
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}
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reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
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reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
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if (state == AMDGPU_IRQ_STATE_DISABLE)
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if (state == AMDGPU_IRQ_STATE_DISABLE)
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WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
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reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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else
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else
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WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
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reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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return 0;
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return 0;
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}
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}
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@ -3320,7 +3303,6 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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struct amdgpu_iv_entry *entry)
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{
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{
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int reg_block;
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unsigned long flags;
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unsigned long flags;
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unsigned crtc_id;
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unsigned crtc_id;
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struct amdgpu_crtc *amdgpu_crtc;
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struct amdgpu_crtc *amdgpu_crtc;
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@ -3329,33 +3311,15 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
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crtc_id = (entry->src_id - 8) >> 1;
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crtc_id = (entry->src_id - 8) >> 1;
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amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
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amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
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/* ack the interrupt */
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if (crtc_id >= adev->mode_info.num_crtc) {
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switch(crtc_id){
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DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
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case AMDGPU_PAGEFLIP_IRQ_D1:
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return -EINVAL;
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reg_block = CRTC0_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D2:
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reg_block = CRTC1_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D3:
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reg_block = CRTC2_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D4:
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reg_block = CRTC3_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D5:
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reg_block = CRTC4_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D6:
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reg_block = CRTC5_REGISTER_OFFSET;
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break;
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default:
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DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
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return -EINVAL;
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}
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}
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if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
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if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
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WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
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GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
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WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
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GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
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/* IRQ could occur when in initial stage */
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/* IRQ could occur when in initial stage */
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if(amdgpu_crtc == NULL)
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if(amdgpu_crtc == NULL)
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@ -3312,37 +3312,20 @@ static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
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unsigned type,
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unsigned type,
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enum amdgpu_interrupt_state state)
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enum amdgpu_interrupt_state state)
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{
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{
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u32 reg, reg_block;
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u32 reg;
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/* now deal with page flip IRQ */
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switch (type) {
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if (type >= adev->mode_info.num_crtc) {
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case AMDGPU_PAGEFLIP_IRQ_D1:
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DRM_ERROR("invalid pageflip crtc %d\n", type);
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reg_block = CRTC0_REGISTER_OFFSET;
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return -EINVAL;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D2:
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reg_block = CRTC1_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D3:
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reg_block = CRTC2_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D4:
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reg_block = CRTC3_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D5:
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reg_block = CRTC4_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D6:
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reg_block = CRTC5_REGISTER_OFFSET;
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break;
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default:
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DRM_ERROR("invalid pageflip crtc %d\n", type);
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return -EINVAL;
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}
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}
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reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
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reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
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if (state == AMDGPU_IRQ_STATE_DISABLE)
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if (state == AMDGPU_IRQ_STATE_DISABLE)
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WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
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reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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else
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else
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WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
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reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
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return 0;
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return 0;
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}
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}
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@ -3351,7 +3334,6 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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struct amdgpu_iv_entry *entry)
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{
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{
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int reg_block;
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unsigned long flags;
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unsigned long flags;
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unsigned crtc_id;
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unsigned crtc_id;
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struct amdgpu_crtc *amdgpu_crtc;
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struct amdgpu_crtc *amdgpu_crtc;
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crtc_id = (entry->src_id - 8) >> 1;
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crtc_id = (entry->src_id - 8) >> 1;
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amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
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amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
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/* ack the interrupt */
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if (crtc_id >= adev->mode_info.num_crtc) {
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switch(crtc_id){
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DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
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case AMDGPU_PAGEFLIP_IRQ_D1:
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return -EINVAL;
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reg_block = CRTC0_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D2:
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reg_block = CRTC1_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D3:
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reg_block = CRTC2_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D4:
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reg_block = CRTC3_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D5:
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reg_block = CRTC4_REGISTER_OFFSET;
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break;
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case AMDGPU_PAGEFLIP_IRQ_D6:
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reg_block = CRTC5_REGISTER_OFFSET;
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break;
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default:
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DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
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return -EINVAL;
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}
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}
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if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
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if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
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WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
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GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
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WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
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GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
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/* IRQ could occur when in initial stage */
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/* IRQ could occur when in initial stage */
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if (amdgpu_crtc == NULL)
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if (amdgpu_crtc == NULL)
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