mvebu fixes for 5.17 (part 2)

Allow using old PCIe card on Armada 37xx
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCYioC+wAKCRALBhiOFHI7
 1YTCAJ9B44SBSCWSGFEBeO/aE6XxT3EbcQCgiMUGAwdvTQ7rYUNiCxc2/In72L4=
 =wqVm
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIqCmoACgkQmmx57+YA
 GNmfmhAAmUeMbp4Z6PpQ2Vj5+INHxf7STMWnCRBtHxWWdlCcglz9sep0ANfuf82D
 ewt7dM5WTRNefoRI3/36lhqBO3TGkycY3XQj+2LEO0DrqOyPGiEOi5iyqWpG9pLc
 hoAPa8Pi7qaxkWQ7yccJi3us8Y6VmdMHEOb3SlTgaJBP88eAVhsdbB7Cgq4RxbXB
 UOdWYAgEje89TNy2g80+zTmVEwS4OHgf3YID1/bB8a7FoLlEJ3N3fnVINRsPVZoO
 yY7a3UuHlnDZGQ6aXTkoteuEXNTPIhM+FMIwbZ+svp6leESruWnVrEbXjnOk4E62
 tPWbL67+YOHahcOH6yXs5xNt70ot/lz6XjpEm9X5+lCtbAfT75eq8YLFRze6jQ+2
 BcFvon89OcTdF7iYEHxR1r+8+oAZ8UwSzEG+kB1IO27hfN7P53cd9WXO76ir4u0j
 voGp+CFC5AjJwpvZd+eTqq/049P18pXZT7iPdP2QgIjMrHnFTGJTzhtY8ca0R61d
 YpS3nYqjgkWb5Xk/BcuPLkVPWxkcQsKxe0u2z1j/S8W2b7GpCVkxH9zK98Im5Jvk
 GEwBGFFN3LhOzX4Ueb9H/q2Ao/DshAKdj3FtkfVEoFRBKS9R8FZx3hACv8vrUJom
 8BzParaqTb4pF2biy3N+Z+1TRlXoqbRGhpZSegpVA/IBM9FwTBY=
 =YxFV
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes

mvebu fixes for 5.17 (part 2)

Allow using old PCIe card on Armada 37xx

* tag 'mvebu-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
  arm64: dts: marvell: armada-37xx: Remap IO space to bus address 0x0

Link: https://lore.kernel.org/r/87bkydj4fn.fsf@BL-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-03-10 15:25:45 +01:00
commit 7e606edaa0
2 changed files with 7 additions and 2 deletions

View file

@ -139,7 +139,9 @@ &pcie0 {
/*
* U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
* contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
* 2 size cells and also expects that the second range starts at 16 MB offset. If these
* 2 size cells and also expects that the second range starts at 16 MB offset. Also it
* expects that first range uses same address for PCI (child) and CPU (parent) cells (so
* no remapping) and that this address is the lowest from all specified ranges. If these
* conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
* space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
* for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
@ -148,6 +150,9 @@ &pcie0 {
* https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
* https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
* https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
* Bug related to requirement of same child and parent addresses for first range is fixed
* in U-Boot version 2022.04 by following commit:
* https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
*/
#address-cells = <3>;
#size-cells = <2>;

View file

@ -499,7 +499,7 @@ pcie0: pcie@d0070000 {
* (totaling 127 MiB) for MEM.
*/
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
0x81000000 0 0xefff0000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,