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spi: mediatek: add ipm design support for MT7986
this patch add the support of ipm design. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220315032411.2826-4-leilk.liu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
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parent
da40a352db
commit
7e963fb2a3
1 changed files with 87 additions and 15 deletions
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@ -31,6 +31,7 @@
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#define SPI_CFG2_REG 0x0028
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#define SPI_TX_SRC_REG_64 0x002c
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#define SPI_RX_DST_REG_64 0x0030
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#define SPI_CFG3_IPM_REG 0x0040
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#define SPI_CFG0_SCK_HIGH_OFFSET 0
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#define SPI_CFG0_SCK_LOW_OFFSET 8
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@ -51,6 +52,7 @@
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#define SPI_CFG1_CS_IDLE_MASK 0xff
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#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
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#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
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#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16)
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#define SPI_CFG2_SCK_HIGH_OFFSET 0
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#define SPI_CFG2_SCK_LOW_OFFSET 16
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@ -71,7 +73,13 @@
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#define SPI_CMD_TX_ENDIAN BIT(15)
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#define SPI_CMD_FINISH_IE BIT(16)
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#define SPI_CMD_PAUSE_IE BIT(17)
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#define SPI_CMD_IPM_NONIDLE_MODE BIT(19)
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#define SPI_CMD_IPM_SPIM_LOOP BIT(21)
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#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22
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#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22)
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#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2)
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#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3)
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#define MT8173_SPI_MAX_PAD_SEL 3
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#define MTK_SPI_PAUSE_INT_STATUS 0x2
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@ -81,6 +89,7 @@
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#define MTK_SPI_MAX_FIFO_SIZE 32U
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#define MTK_SPI_PACKET_SIZE 1024
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#define MTK_SPI_IPM_PACKET_SIZE SZ_64K
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#define MTK_SPI_32BITS_MASK (0xffffffff)
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#define DMA_ADDR_EXT_BITS (36)
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@ -96,6 +105,9 @@ struct mtk_spi_compatible {
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bool dma_ext;
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/* some IC no need unprepare SPI clk */
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bool no_need_unprepare;
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/* IPM design adjust and extend register to support more features */
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bool ipm_design;
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};
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struct mtk_spi {
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@ -119,6 +131,12 @@ static const struct mtk_spi_compatible mt2712_compat = {
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.must_tx = true,
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};
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static const struct mtk_spi_compatible mtk_ipm_compat = {
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.enhance_timing = true,
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.dma_ext = true,
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.ipm_design = true,
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};
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static const struct mtk_spi_compatible mt6765_compat = {
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.need_pad_sel = true,
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.must_tx = true,
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@ -160,6 +178,9 @@ static const struct mtk_chip_config mtk_default_chip_info = {
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};
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static const struct of_device_id mtk_spi_of_match[] = {
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{ .compatible = "mediatek,spi-ipm",
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.data = (void *)&mtk_ipm_compat,
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},
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{ .compatible = "mediatek,mt2701-spi",
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.data = (void *)&mtk_common_compat,
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},
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@ -278,12 +299,11 @@ static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
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return 0;
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}
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static int mtk_spi_prepare_message(struct spi_master *master,
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struct spi_message *msg)
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static int mtk_spi_hw_init(struct spi_master *master,
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struct spi_device *spi)
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{
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u16 cpha, cpol;
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u32 reg_val;
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struct spi_device *spi = msg->spi;
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struct mtk_chip_config *chip_config = spi->controller_data;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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@ -291,6 +311,15 @@ static int mtk_spi_prepare_message(struct spi_master *master,
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cpol = spi->mode & SPI_CPOL ? 1 : 0;
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reg_val = readl(mdata->base + SPI_CMD_REG);
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if (mdata->dev_comp->ipm_design) {
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/* SPI transfer without idle time until packet length done */
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reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
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if (spi->mode & SPI_LOOP)
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reg_val |= SPI_CMD_IPM_SPIM_LOOP;
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else
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reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
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}
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if (cpha)
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reg_val |= SPI_CMD_CPHA;
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else
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@ -348,23 +377,39 @@ static int mtk_spi_prepare_message(struct spi_master *master,
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mdata->base + SPI_PAD_SEL_REG);
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/* tick delay */
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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if (mdata->dev_comp->enhance_timing) {
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reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
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reg_val |= ((chip_config->tick_delay & 0x7)
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<< SPI_CFG1_GET_TICK_DLY_OFFSET);
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if (mdata->dev_comp->ipm_design) {
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reg_val = readl(mdata->base + SPI_CMD_REG);
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reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
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reg_val |= ((chip_config->tick_delay & 0x7)
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<< SPI_CMD_IPM_GET_TICKDLY_OFFSET);
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writel(reg_val, mdata->base + SPI_CMD_REG);
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} else {
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
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reg_val |= ((chip_config->tick_delay & 0x7)
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<< SPI_CFG1_GET_TICK_DLY_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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}
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} else {
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
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reg_val |= ((chip_config->tick_delay & 0x3)
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<< SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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}
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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/* set hw cs timing */
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mtk_spi_set_hw_cs_timing(spi);
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return 0;
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}
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static int mtk_spi_prepare_message(struct spi_master *master,
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struct spi_message *msg)
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{
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return mtk_spi_hw_init(master, msg->spi);
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}
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static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
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{
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u32 reg_val;
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@ -386,13 +431,13 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
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}
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static void mtk_spi_prepare_transfer(struct spi_master *master,
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struct spi_transfer *xfer)
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u32 speed_hz)
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{
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u32 div, sck_time, reg_val;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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if (xfer->speed_hz < mdata->spi_clk_hz / 2)
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div = DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz);
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if (speed_hz < mdata->spi_clk_hz / 2)
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div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz);
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else
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div = 1;
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@ -423,12 +468,24 @@ static void mtk_spi_setup_packet(struct spi_master *master)
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u32 packet_size, packet_loop, reg_val;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
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if (mdata->dev_comp->ipm_design)
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packet_size = min_t(u32,
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mdata->xfer_len,
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MTK_SPI_IPM_PACKET_SIZE);
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else
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packet_size = min_t(u32,
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mdata->xfer_len,
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MTK_SPI_PACKET_SIZE);
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packet_loop = mdata->xfer_len / packet_size;
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
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if (mdata->dev_comp->ipm_design)
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reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
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else
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reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
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reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
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reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
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reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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}
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@ -523,7 +580,7 @@ static int mtk_spi_fifo_transfer(struct spi_master *master,
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mdata->cur_transfer = xfer;
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mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
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mdata->num_xfered = 0;
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mtk_spi_prepare_transfer(master, xfer);
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mtk_spi_prepare_transfer(master, xfer->speed_hz);
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mtk_spi_setup_packet(master);
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if (xfer->tx_buf) {
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@ -556,7 +613,7 @@ static int mtk_spi_dma_transfer(struct spi_master *master,
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mdata->cur_transfer = xfer;
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mdata->num_xfered = 0;
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mtk_spi_prepare_transfer(master, xfer);
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mtk_spi_prepare_transfer(master, xfer->speed_hz);
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cmd = readl(mdata->base + SPI_CMD_REG);
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if (xfer->tx_buf)
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@ -591,6 +648,19 @@ static int mtk_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
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u32 reg_val = 0;
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/* prepare xfer direction and duplex mode */
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if (mdata->dev_comp->ipm_design) {
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if (!xfer->tx_buf || !xfer->rx_buf) {
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reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
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if (xfer->rx_buf)
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reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
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}
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writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
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}
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if (master->can_dma(master, spi, xfer))
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return mtk_spi_dma_transfer(master, spi, xfer);
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else
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@ -757,6 +827,8 @@ static int mtk_spi_probe(struct platform_device *pdev)
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if (mdata->dev_comp->must_tx)
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master->flags = SPI_MASTER_MUST_TX;
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if (mdata->dev_comp->ipm_design)
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master->mode_bits |= SPI_LOOP;
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if (mdata->dev_comp->need_pad_sel) {
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mdata->pad_num = of_property_count_u32_elems(
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