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drm/amd/display: Update P010 scaling cap

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[ Upstream commit 038c532346 ]

[Why]
Keep the same as previous APU and also insert clock dump

Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stable-dep-of: f341055b10 ("drm/amd/display: Send DTBCLK disable message on first commit")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Charlene Liu 2024-01-03 17:09:30 -05:00 committed by Greg Kroah-Hartman
parent 8feb1652af
commit 7ea8a0e120
2 changed files with 13 additions and 14 deletions
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25
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
View file

@ -384,19 +384,6 @@ static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base)
dcn35_smu_enable_pme_wa(clk_mgr); dcn35_smu_enable_pme_wa(clk_mgr);
} }
void dcn35_init_clocks(struct clk_mgr *clk_mgr)
{
uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
// Assumption is that boot state always supports pstate
clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
clk_mgr->clks.p_state_change_support = true;
clk_mgr->clks.prev_p_state_change_support = true;
clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
}
bool dcn35_are_clock_states_equal(struct dc_clocks *a, bool dcn35_are_clock_states_equal(struct dc_clocks *a,
struct dc_clocks *b) struct dc_clocks *b)
@ -421,7 +408,19 @@ static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs
struct clk_mgr_dcn35 *clk_mgr) struct clk_mgr_dcn35 *clk_mgr)
{ {
} }
void dcn35_init_clocks(struct clk_mgr *clk_mgr)
{
uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
// Assumption is that boot state always supports pstate
clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
clk_mgr->clks.p_state_change_support = true;
clk_mgr->clks.prev_p_state_change_support = true;
clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
}
static struct clk_bw_params dcn35_bw_params = { static struct clk_bw_params dcn35_bw_params = {
.vram_type = Ddr4MemType, .vram_type = Ddr4MemType,
.num_channels = 1, .num_channels = 1,

2
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
View file

@ -701,7 +701,7 @@ static const struct dc_plane_cap plane_cap = {
// 6:1 downscaling ratio: 1000/6 = 166.666 // 6:1 downscaling ratio: 1000/6 = 166.666
.max_downscale_factor = { .max_downscale_factor = {
.argb8888 = 167, .argb8888 = 250,
.nv12 = 167, .nv12 = 167,
.fp16 = 167 .fp16 = 167
}, },