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drivers: net: xgene: Add workaround for errata 10GE_1
This patch implements workaround for errata 10GE_1: 10Gb Ethernet port FIFO threshold default values are incorrect. Signed-off-by: Quan Nguyen <qnguyen@apm.com> Signed-off-by: Toan Le <toanle@apm.com> Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Tested-by: Fushen Chen <fchen@apm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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2 changed files with 12 additions and 0 deletions
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@ -341,8 +341,15 @@ static void xgene_xgmac_init(struct xgene_enet_pdata *pdata)
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xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);
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data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
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/* Errata 10GE_1 - FIFO threshold default value incorrect */
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RSIF_CLE_BUFF_THRESH_SET(&data, XG_RSIF_CLE_BUFF_THRESH);
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xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data);
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/* Errata 10GE_1 - FIFO threshold default value incorrect */
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xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, &data);
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RSIF_PLC_CLE_BUFF_THRESH_SET(&data, XG_RSIF_PLC_CLE_BUFF_THRESH);
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xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, data);
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xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data);
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data |= BIT(12);
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xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data);
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@ -65,6 +65,11 @@
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#define XG_DEF_PAUSE_THRES 0x390
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#define XG_DEF_PAUSE_OFF_THRES 0x2c0
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#define XG_RSIF_CONFIG_REG_ADDR 0x00a0
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#define XG_RSIF_CLE_BUFF_THRESH 0x3
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#define RSIF_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 3)
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#define XG_RSIF_CONFIG1_REG_ADDR 0x00b8
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#define XG_RSIF_PLC_CLE_BUFF_THRESH 0x1
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#define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2)
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#define XCLE_BYPASS_REG0_ADDR 0x0160
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#define XCLE_BYPASS_REG1_ADDR 0x0164
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#define XG_CFG_BYPASS_ADDR 0x0204
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