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Qualcomm ARM64 DT fixes for v5.19
This removes duplicate includes in the sc7180-trogdor files, which accidentally ended up disabling nodes intended to be enabled. It corrects identifiers for CPU6/7 on MSM8994. On SM8450 the UFS node's interconnects property is updated to match the #interconnect-cells, avoiding sync_state issues and the GIC ITS is defined, to correct the references from the PCIe nodes. On SDM845 the display subsystem's AHB clock is corrected and on msm8992 devices, the supplies for lvs 1 and 2 are correctly specified. Lastly, a welcome addition of Konrad as reviewer for the Qualcomm SoC. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmLBBmobHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FuvsQAKP6BXA5FQ13nHdfFh38 kgNdw93SIn49MW7jxHbnYRXxxW0j1SxxipQAZmlfChE3qptfjzaQcdtN/AboNLi8 sBT03vjoMPysoe9aLOEY3BLCsM/qB3AiP5jXEahu8P3RbU6cY69W8mUEoZhzBi3H Cow0g0zg37R48W7DZkh+B0rDzFk48TGzbnrBCwrJ4PF3cciNVKZOWmBMA3Vm0741 vckIU1WCff3v56ZyAusv4wmDBq5Y0K5/PCx4xz3qoFXBXoH27I0XxywXgbb2tmtH MqxeOjS+hwJePW3dqMs2h09z0Uf5NT2cgoobCMkNOl3j/0Dwrn0zINRxBVNCLVDq h084fcFxKqQWWbN+SDO5QUIyPgAs/XVyG8nzEXE19XftOIu9NGfTBOYZZ2kWGZCM IJIFfvxm6Xh73dd0afDRRMbxZrpLaBrq0vz4jF3A3Ycs7r5JEgsz18H1yo/YzGX0 sXlTdTBUEaHZnfhQNfsNdVXaFcXWu0gLmH/sh7nRd++9Gl4d0r0Ro9Q/ZYfThsRI vWQWuhLq15JL2c/qGxK/BTHIdN/+d4v3pr5CirM+ijKUZjzyAsB6e6i6gf4WNEUi EdDf3Sj7IWOIAx4/80Xg+r+4MfCW5ZWKGSxIlpYFX83bSh2uM2Zopjiwg1qxw70k RgtLmTxsC22YnwWcks49OjWV =sObb -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLB/d8ACgkQmmx57+YA GNniWw/+NMqJ3hrizjmDS3sk2feWr6fU96gGYZ8myD/Qkw/5Kx3tOztf6mvU2SHm SGWyhIT72SalATxyH0EDzrx8UG/wcdXXN/3xwTnLS5BtwgqdjcltV33zD3WvcQVu Waswso1ULQH9NyWib+1aB5fFGJNUMtqWvGLBUJO2gQNphojTpICdHJKbe8B/VzXY z5n/3yOiaoOdpjy2p65Fi6LTlEmeZY5NtiZL5aIw83728eJILcLmX0vjtuGvG3df qp8HmFDhTYimQVqQC9bhG84lQSyGsos8/4ntxiYZddgL1ukmRRFb8ZAk9Vbvqkb8 8RK8v7J75uKFF0SIQ8j0OOHN/J7SrrTCuvUlE+pjL+HpTFMwJm+wlPAvPUZl3Szg nMIExwZHklnzkW+mqTeQGm/RFzErAXPARuu4pmgy+6J01Az29qNq5S7TiszxKbSm cTPaPZCNLvAAHsZ4VudG6wzT56QB8NEv6ktvKELQ+e74x9AYe+unn3Url1vCTir6 QjT/A3EoPf8bMQJAJNXMDOThVU7RNBEvi1kli8H6vGqvnTCedRCovso/ntAyvyF3 dTV1CHIjVo9f/LN8TrxBIj2mUl4u0dGT5JCtQXWqJNKprkrXLOdH7I5DsVwAcJkY pWWpf8Nr1yMWSBa2gRs5zhR9dq0xJK8HX3+E5OfbN5Wum7AKrkw= =+pwl -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-fixes-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes Qualcomm ARM64 DT fixes for v5.19 This removes duplicate includes in the sc7180-trogdor files, which accidentally ended up disabling nodes intended to be enabled. It corrects identifiers for CPU6/7 on MSM8994. On SM8450 the UFS node's interconnects property is updated to match the #interconnect-cells, avoiding sync_state issues and the GIC ITS is defined, to correct the references from the PCIe nodes. On SDM845 the display subsystem's AHB clock is corrected and on msm8992 devices, the supplies for lvs 1 and 2 are correctly specified. Lastly, a welcome addition of Konrad as reviewer for the Qualcomm SoC. * tag 'qcom-arm64-fixes-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: dts: qcom: msm8992-*: Fix vdd_lvs1_2-supply typo MAINTAINERS: Add myself as a reviewer for Qualcomm ARM/64 support arm64: dts: qcom: sdm845: use dispcc AHB clock for mdss node arm64: dts: qcom: sm8450 add ITS device tree node arm64: dts: qcom: msm8994: Fix CPU6/7 reg values arm64: dts: qcom: sm8450: fix interconnects property of UFS node arm64: dts: qcom: Remove duplicate sc7180-trogdor include on lazor/homestar Link: https://lore.kernel.org/r/20220703030208.408109-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
7ecd8a7af3
8 changed files with 20 additions and 9 deletions
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@ -2540,6 +2540,7 @@ W: http://www.armlinux.org.uk/
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ARM/QUALCOMM SUPPORT
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M: Andy Gross <agross@kernel.org>
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M: Bjorn Andersson <bjorn.andersson@linaro.org>
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R: Konrad Dybcio <konrad.dybcio@somainline.org>
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L: linux-arm-msm@vger.kernel.org
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S: Maintained
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
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@ -74,7 +74,7 @@ pm8994_regulators: pm8994-regulators {
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vdd_l17_29-supply = <&vph_pwr>;
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vdd_l20_21-supply = <&vph_pwr>;
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vdd_l25-supply = <&pm8994_s5>;
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vdd_lvs1_2 = <&pm8994_s4>;
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vdd_lvs1_2-supply = <&pm8994_s4>;
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/* S1, S2, S6 and S12 are managed by RPMPD */
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@ -171,7 +171,7 @@ pm8994-regulators {
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vdd_l17_29-supply = <&vph_pwr>;
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vdd_l20_21-supply = <&vph_pwr>;
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vdd_l25-supply = <&pm8994_s5>;
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vdd_lvs1_2 = <&pm8994_s4>;
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vdd_lvs1_2-supply = <&pm8994_s4>;
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/* S1, S2, S6 and S12 are managed by RPMPD */
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@ -100,7 +100,7 @@ CPU5: cpu@101 {
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CPU6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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reg = <0x0 0x102>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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};
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@ -108,7 +108,7 @@ CPU6: cpu@102 {
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CPU7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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reg = <0x0 0x103>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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};
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@ -5,7 +5,7 @@
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* Copyright 2021 Google LLC.
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*/
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#include "sc7180-trogdor.dtsi"
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/* This file must be included after sc7180-trogdor.dtsi */
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/ {
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/* BOARD-SPECIFIC TOP LEVEL NODES */
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@ -5,7 +5,7 @@
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* Copyright 2020 Google LLC.
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*/
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#include "sc7180-trogdor.dtsi"
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/* This file must be included after sc7180-trogdor.dtsi */
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&ap_sar_sensor {
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semtech,cs0-ground;
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@ -4244,7 +4244,7 @@ mdss: mdss@ae00000 {
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power-domains = <&dispcc MDSS_GDSC>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface", "core";
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@ -2853,6 +2853,16 @@ intc: interrupt-controller@17100000 {
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reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
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<0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic_its: msi-controller@17140000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x17140000 0x0 0x20000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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timer@17420000 {
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@ -3037,8 +3047,8 @@ ufs_mem_hc: ufshc@1d84000 {
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iommus = <&apps_smmu 0xe0 0x0>;
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interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
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interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
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interconnect-names = "ufs-ddr", "cpu-ufs";
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clock-names =
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"core_clk",
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