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drm/i915: Preallocate the debug power domain wakerefs array
Since the current size of intel_display_power_domain_set struct is close to 1kB, it's better to use preallocated memory for it. The only user of the intel_display_power_get/put_in_set() allocating the struct on stack is hsw_get_pipe_config(), so we can avoid potential stack overallocations by moving the struct here to the preallocated intel_crtc struct (hsw_get_pipe_config() is non-reentrant wrt. each CRTC). This patch replaces https://lore.kernel.org/intel-gfx/20221107170917.3566758-5-imre.deak@intel.com/T/#md3f6cdf17fcd Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221114122251.21327-3-imre.deak@intel.com
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10b85f0e1d
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7ed310025e
2 changed files with 6 additions and 6 deletions
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@ -4051,20 +4051,19 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_display_power_domain_set power_domain_set = { };
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bool active;
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u32 tmp;
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if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
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if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
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POWER_DOMAIN_PIPE(crtc->pipe)))
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return false;
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pipe_config->shared_dpll = NULL;
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active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
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active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
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if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
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bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
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bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
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drm_WARN_ON(&dev_priv->drm, active);
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active = true;
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}
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@ -4123,7 +4122,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
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pipe_config->ips_linetime =
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REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
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if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
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if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
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POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
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if (DISPLAY_VER(dev_priv) >= 9)
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skl_get_pfit_config(pipe_config);
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@ -4154,7 +4153,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
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}
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out:
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intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
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intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
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return active;
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}
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@ -1375,6 +1375,7 @@ struct intel_crtc {
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u16 vmax_vblank_start;
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struct intel_display_power_domain_set enabled_power_domains;
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struct intel_display_power_domain_set hw_readout_power_domains;
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struct intel_overlay *overlay;
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struct intel_crtc_state *config;
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