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dt-bindings: update risc-v cpu properties
The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip version using a draft verion of the RISC-V ISA specifications. To avoid any confusion with CPU cores using stable specifications, add the compatible string "canaan,k210" for this SoC CPU cores. Also add the "riscv,none" value to the mmu-type property to allow a DT to indicate that the CPU being described does not have an MMU or that it has an MMU that is not usable (which is the case for the K210 SoC). Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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@ -39,6 +39,7 @@ properties:
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- sifive,u74
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- sifive,u5
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- sifive,u7
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- canaan,k210
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- const: riscv
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- const: riscv # Simulator only
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description:
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@ -56,6 +57,7 @@ properties:
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- riscv,sv32
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- riscv,sv39
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- riscv,sv48
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- riscv,none
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riscv,isa:
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description:
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