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ARM: at91: dt: at91sam9x5: complete NAND pinctrl
There was only chip enable and readdy/busy pins for the nand controller. This add the rest of the pins. pinctrl_nand_16bits contains the specific muxes for 16 bits NANDs. Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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1 changed files with 26 additions and 2 deletions
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@ -238,8 +238,32 @@ pinctrl_uart1: uart1-0 {
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nand {
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pinctrl_nand: nand-0 {
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atmel,pins =
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<3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */
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3 5 0x0 0x1>; /* PD5 gpio RDY/BUSY pin pull_up */
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<3 0 0x1 0x0 /* PD0 periph A Read Enable */
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3 1 0x1 0x0 /* PD1 periph A Write Enable */
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3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */
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3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */
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3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */
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3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */
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3 6 0x1 0x0 /* PD6 periph A Data bit 0 */
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3 7 0x1 0x0 /* PD7 periph A Data bit 1 */
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3 8 0x1 0x0 /* PD8 periph A Data bit 2 */
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3 9 0x1 0x0 /* PD9 periph A Data bit 3 */
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3 10 0x1 0x0 /* PD10 periph A Data bit 4 */
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3 11 0x1 0x0 /* PD11 periph A Data bit 5 */
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3 12 0x1 0x0 /* PD12 periph A Data bit 6 */
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3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */
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};
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pinctrl_nand_16bits: nand_16bits-0 {
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atmel,pins =
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<3 14 0x1 0x0 /* PD14 periph A Data bit 8 */
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3 15 0x1 0x0 /* PD15 periph A Data bit 9 */
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3 16 0x1 0x0 /* PD16 periph A Data bit 10 */
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3 17 0x1 0x0 /* PD17 periph A Data bit 11 */
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3 18 0x1 0x0 /* PD18 periph A Data bit 12 */
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3 19 0x1 0x0 /* PD19 periph A Data bit 13 */
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3 20 0x1 0x0 /* PD20 periph A Data bit 14 */
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3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */
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};
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};
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