powerpc/powernv: Introduce new PHB type for opencapi links
The NPU was already abstracted by opal as a virtual PHB for nvlink, but it helps to be able to differentiate between a nvlink or opencapi PHB, as it's not completely transparent to linux. In particular, PE assignment differs and we'll also need the information in later patches. So rename existing PNV_PHB_NPU type to PNV_PHB_NPU_NVLINK and add a new type PNV_PHB_NPU_OCAPI. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -277,7 +277,7 @@ static int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe)
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int64_t rc = 0;
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int64_t rc = 0;
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phys_addr_t top = memblock_end_of_DRAM();
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phys_addr_t top = memblock_end_of_DRAM();
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if (phb->type != PNV_PHB_NPU || !npe->pdev)
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if (phb->type != PNV_PHB_NPU_NVLINK || !npe->pdev)
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return -EINVAL;
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return -EINVAL;
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rc = pnv_npu_unset_window(npe, 0);
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rc = pnv_npu_unset_window(npe, 0);
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@ -54,7 +54,8 @@
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#define POWERNV_IOMMU_DEFAULT_LEVELS 1
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#define POWERNV_IOMMU_DEFAULT_LEVELS 1
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#define POWERNV_IOMMU_MAX_LEVELS 5
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#define POWERNV_IOMMU_MAX_LEVELS 5
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static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
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static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
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"NPU_OCAPI" };
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static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
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static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
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void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
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void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
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@ -933,7 +934,7 @@ static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
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* Configure PELTV. NPUs don't have a PELTV table so skip
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* Configure PELTV. NPUs don't have a PELTV table so skip
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* configuration on them.
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* configuration on them.
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*/
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*/
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if (phb->type != PNV_PHB_NPU)
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if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
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pnv_ioda_set_peltv(phb, pe, true);
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pnv_ioda_set_peltv(phb, pe, true);
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/* Setup reverse map */
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/* Setup reverse map */
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@ -1281,16 +1282,23 @@ static void pnv_pci_ioda_setup_PEs(void)
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{
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{
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struct pci_controller *hose, *tmp;
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struct pci_controller *hose, *tmp;
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struct pnv_phb *phb;
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struct pnv_phb *phb;
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struct pci_bus *bus;
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struct pci_dev *pdev;
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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phb = hose->private_data;
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phb = hose->private_data;
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if (phb->type == PNV_PHB_NPU) {
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if (phb->type == PNV_PHB_NPU_NVLINK) {
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/* PE#0 is needed for error reporting */
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/* PE#0 is needed for error reporting */
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pnv_ioda_reserve_pe(phb, 0);
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pnv_ioda_reserve_pe(phb, 0);
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pnv_ioda_setup_npu_PEs(hose->bus);
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pnv_ioda_setup_npu_PEs(hose->bus);
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if (phb->model == PNV_PHB_MODEL_NPU2)
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if (phb->model == PNV_PHB_MODEL_NPU2)
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pnv_npu2_init(phb);
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pnv_npu2_init(phb);
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}
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}
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if (phb->type == PNV_PHB_NPU_OCAPI) {
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bus = hose->bus;
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list_for_each_entry(pdev, &bus->devices, bus_list)
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pnv_ioda_setup_dev_PE(pdev);
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}
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}
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}
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}
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}
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@ -2648,7 +2656,7 @@ static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
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hose = pci_bus_to_host(pdev->bus);
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hose = pci_bus_to_host(pdev->bus);
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phb = hose->private_data;
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phb = hose->private_data;
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if (phb->type != PNV_PHB_NPU)
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if (phb->type != PNV_PHB_NPU_NVLINK)
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return 0;
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return 0;
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*ptmppe = &phb->ioda.pe_array[pdn->pe_number];
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*ptmppe = &phb->ioda.pe_array[pdn->pe_number];
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@ -2732,7 +2740,7 @@ static void pnv_pci_ioda_setup_iommu_api(void)
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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phb = hose->private_data;
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phb = hose->private_data;
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if (phb->type != PNV_PHB_NPU)
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if (phb->type != PNV_PHB_NPU_NVLINK)
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continue;
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continue;
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list_for_each_entry(pe, &phb->ioda.pe_list, list) {
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list_for_each_entry(pe, &phb->ioda.pe_list, list) {
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@ -3782,6 +3790,13 @@ static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
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.shutdown = pnv_pci_ioda_shutdown,
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.shutdown = pnv_pci_ioda_shutdown,
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};
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};
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static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
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.enable_device_hook = pnv_pci_enable_device_hook,
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.window_alignment = pnv_pci_window_alignment,
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.reset_secondary_bus = pnv_pci_reset_secondary_bus,
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.shutdown = pnv_pci_ioda_shutdown,
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};
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#ifdef CONFIG_CXL_BASE
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#ifdef CONFIG_CXL_BASE
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const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
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const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
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.dma_dev_setup = pnv_pci_dma_dev_setup,
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.dma_dev_setup = pnv_pci_dma_dev_setup,
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@ -4015,9 +4030,14 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
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*/
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*/
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ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
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ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
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if (phb->type == PNV_PHB_NPU) {
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switch (phb->type) {
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case PNV_PHB_NPU_NVLINK:
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hose->controller_ops = pnv_npu_ioda_controller_ops;
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hose->controller_ops = pnv_npu_ioda_controller_ops;
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} else {
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break;
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case PNV_PHB_NPU_OCAPI:
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hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
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break;
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default:
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phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
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phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
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hose->controller_ops = pnv_pci_ioda_controller_ops;
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hose->controller_ops = pnv_pci_ioda_controller_ops;
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}
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}
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@ -4063,7 +4083,12 @@ void __init pnv_pci_init_ioda2_phb(struct device_node *np)
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void __init pnv_pci_init_npu_phb(struct device_node *np)
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void __init pnv_pci_init_npu_phb(struct device_node *np)
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{
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{
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pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
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pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
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}
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void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
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{
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pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
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}
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}
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void __init pnv_pci_init_ioda_hub(struct device_node *np)
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void __init pnv_pci_init_ioda_hub(struct device_node *np)
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@ -1142,6 +1142,10 @@ void __init pnv_pci_init(void)
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for_each_compatible_node(np, NULL, "ibm,ioda2-npu2-phb")
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for_each_compatible_node(np, NULL, "ibm,ioda2-npu2-phb")
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pnv_pci_init_npu_phb(np);
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pnv_pci_init_npu_phb(np);
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/* Look for NPU2 OpenCAPI PHBs */
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for_each_compatible_node(np, NULL, "ibm,ioda2-npu2-opencapi-phb")
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pnv_pci_init_npu2_opencapi_phb(np);
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/* Configure IOMMU DMA hooks */
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/* Configure IOMMU DMA hooks */
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set_pci_dma_ops(&dma_iommu_ops);
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set_pci_dma_ops(&dma_iommu_ops);
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}
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}
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@ -12,9 +12,10 @@ struct pci_dn;
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#define NV_NMMU_ATSD_REGS 8
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#define NV_NMMU_ATSD_REGS 8
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enum pnv_phb_type {
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enum pnv_phb_type {
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PNV_PHB_IODA1 = 0,
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PNV_PHB_IODA1 = 0,
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PNV_PHB_IODA2 = 1,
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PNV_PHB_IODA2 = 1,
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PNV_PHB_NPU = 2,
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PNV_PHB_NPU_NVLINK = 2,
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PNV_PHB_NPU_OCAPI = 3,
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};
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};
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/* Precise PHB model for error management */
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/* Precise PHB model for error management */
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@ -227,6 +228,7 @@ extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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extern void pnv_pci_init_ioda_hub(struct device_node *np);
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extern void pnv_pci_init_ioda_hub(struct device_node *np);
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extern void pnv_pci_init_ioda2_phb(struct device_node *np);
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extern void pnv_pci_init_ioda2_phb(struct device_node *np);
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extern void pnv_pci_init_npu_phb(struct device_node *np);
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extern void pnv_pci_init_npu_phb(struct device_node *np);
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extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
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extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
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extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
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extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
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extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
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