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drm/amd/pm: Show updated clocks on aldebaran
When GFXCLK range is updated in manual/determinism mode, show the updated min/max clock range. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 41 additions and 11 deletions
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@ -78,6 +78,8 @@
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#define smnPCIE_ESM_CTRL 0x111003D0
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#define CLOCK_VALID (1 << 31)
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static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
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MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
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MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
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@ -673,6 +675,7 @@ static int aldebaran_print_clk_levels(struct smu_context *smu,
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struct smu_13_0_dpm_context *dpm_context = NULL;
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uint32_t display_levels;
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uint32_t freq_values[3] = {0};
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uint32_t min_clk, max_clk;
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if (amdgpu_ras_intr_triggered())
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return snprintf(buf, PAGE_SIZE, "unavailable\n");
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@ -700,12 +703,20 @@ static int aldebaran_print_clk_levels(struct smu_context *smu,
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display_levels = clocks.num_levels;
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min_clk = smu->gfx_actual_hard_min_freq & CLOCK_VALID ?
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smu->gfx_actual_hard_min_freq & ~CLOCK_VALID :
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single_dpm_table->dpm_levels[0].value;
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max_clk = smu->gfx_actual_soft_max_freq & CLOCK_VALID ?
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smu->gfx_actual_soft_max_freq & ~CLOCK_VALID :
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single_dpm_table->dpm_levels[1].value;
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freq_values[0] = min_clk;
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freq_values[1] = max_clk;
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/* fine-grained dpm has only 2 levels */
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if (now > single_dpm_table->dpm_levels[0].value &&
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now < single_dpm_table->dpm_levels[1].value) {
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if (now > min_clk && now < max_clk) {
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display_levels = clocks.num_levels + 1;
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freq_values[0] = single_dpm_table->dpm_levels[0].value;
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freq_values[2] = single_dpm_table->dpm_levels[1].value;
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freq_values[2] = max_clk;
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freq_values[1] = now;
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}
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@ -715,12 +726,15 @@ static int aldebaran_print_clk_levels(struct smu_context *smu,
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*/
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if (display_levels == clocks.num_levels) {
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for (i = 0; i < clocks.num_levels; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n", i,
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clocks.data[i].clocks_in_khz / 1000,
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(clocks.num_levels == 1) ? "*" :
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size += sprintf(
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buf + size, "%d: %uMhz %s\n", i,
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freq_values[i],
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(clocks.num_levels == 1) ?
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"*" :
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(aldebaran_freqs_in_same_level(
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clocks.data[i].clocks_in_khz / 1000,
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now) ? "*" : ""));
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freq_values[i], now) ?
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"*" :
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""));
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} else {
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for (i = 0; i < display_levels; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n", i,
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@ -1120,6 +1134,9 @@ static int aldebaran_set_performance_level(struct smu_context *smu,
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&& (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
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smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
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/* Reset user min/max gfx clock */
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smu->gfx_actual_hard_min_freq = 0;
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smu->gfx_actual_soft_max_freq = 0;
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switch (level) {
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@ -1161,7 +1178,14 @@ static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
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if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
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min_clk = max(min, dpm_context->dpm_tables.gfx_table.min);
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max_clk = min(max, dpm_context->dpm_tables.gfx_table.max);
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return smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
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ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
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min_clk, max_clk);
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if (!ret) {
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smu->gfx_actual_hard_min_freq = min_clk | CLOCK_VALID;
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smu->gfx_actual_soft_max_freq = max_clk | CLOCK_VALID;
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}
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return ret;
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}
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if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
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@ -1181,9 +1205,15 @@ static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
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ret = smu_cmn_send_smc_msg_with_param(smu,
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SMU_MSG_EnableDeterminism,
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max, NULL);
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if (ret)
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if (ret) {
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dev_err(adev->dev,
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"Failed to enable determinism at GFX clock %d MHz\n", max);
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} else {
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smu->gfx_actual_hard_min_freq =
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min_clk | CLOCK_VALID;
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smu->gfx_actual_soft_max_freq =
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max | CLOCK_VALID;
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}
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}
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}
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