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[ARM] Orion: distinguish between physical and virtual addresses
Hack up the Orion port to distinguish between virtual and physical addresses of register windows. This will allow moving virtual mappings higher up in the address space, to free up more kernel virtual address space. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
This commit is contained in:
Lennert Buytenhek
Nicolas Pitre
parent
27cd3ad231
commit
7f74c2c7f7
13 changed files with 134 additions and 110 deletions
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@ -265,15 +265,15 @@ void __init orion_setup_cpu_wins(void)
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}
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/*
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* Setup windows for PCI+PCIE IO+MAM space
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* Setup windows for PCI+PCIe IO+MEM space.
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*/
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orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE,
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ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP);
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orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE,
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ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP);
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orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE,
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orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
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ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
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orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
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ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
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orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
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ORION_PCIE_MEM_SIZE, -1);
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orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE,
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orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
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ORION_PCI_MEM_SIZE, -1);
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}
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@ -27,26 +27,26 @@
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****************************************************************************/
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static struct map_desc orion_io_desc[] __initdata = {
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{
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.virtual = ORION_REGS_BASE,
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.pfn = __phys_to_pfn(ORION_REGS_BASE),
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.virtual = ORION_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE),
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.length = ORION_REGS_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = ORION_PCIE_IO_BASE,
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.pfn = __phys_to_pfn(ORION_PCIE_IO_BASE),
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.virtual = ORION_PCIE_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE),
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.length = ORION_PCIE_IO_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = ORION_PCI_IO_BASE,
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.pfn = __phys_to_pfn(ORION_PCI_IO_BASE),
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.virtual = ORION_PCI_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE),
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.length = ORION_PCI_IO_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = ORION_PCIE_WA_BASE,
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.pfn = __phys_to_pfn(ORION_PCIE_WA_BASE),
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.virtual = ORION_PCIE_WA_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE),
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.length = ORION_PCIE_WA_SIZE,
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.type = MT_DEVICE
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},
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@ -63,8 +63,8 @@ void __init orion_map_io(void)
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static struct resource orion_uart_resources[] = {
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{
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.start = UART0_BASE,
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.end = UART0_BASE + 0xff,
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.start = UART0_PHYS_BASE,
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.end = UART0_PHYS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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{
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@ -73,8 +73,8 @@ static struct resource orion_uart_resources[] = {
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = UART1_BASE,
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.end = UART1_BASE + 0xff,
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.start = UART1_PHYS_BASE,
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.end = UART1_PHYS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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{
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@ -86,8 +86,8 @@ static struct resource orion_uart_resources[] = {
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static struct plat_serial8250_port orion_uart_data[] = {
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{
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.mapbase = UART0_BASE,
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.membase = (char *)UART0_BASE,
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.mapbase = UART0_PHYS_BASE,
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.membase = (char *)UART0_VIRT_BASE,
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.irq = IRQ_ORION_UART0,
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.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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@ -95,8 +95,8 @@ static struct plat_serial8250_port orion_uart_data[] = {
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.uartclk = ORION_TCLK,
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},
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{
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.mapbase = UART1_BASE,
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.membase = (char *)UART1_BASE,
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.mapbase = UART1_PHYS_BASE,
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.membase = (char *)UART1_VIRT_BASE,
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.irq = IRQ_ORION_UART1,
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.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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@ -122,8 +122,8 @@ static struct platform_device orion_uart = {
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static struct resource orion_ehci0_resources[] = {
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{
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.start = ORION_USB0_REG_BASE,
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.end = ORION_USB0_REG_BASE + SZ_4K,
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.start = ORION_USB0_PHYS_BASE,
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.end = ORION_USB0_PHYS_BASE + SZ_4K,
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.flags = IORESOURCE_MEM,
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},
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{
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@ -135,8 +135,8 @@ static struct resource orion_ehci0_resources[] = {
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static struct resource orion_ehci1_resources[] = {
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{
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.start = ORION_USB1_REG_BASE,
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.end = ORION_USB1_REG_BASE + SZ_4K,
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.start = ORION_USB1_PHYS_BASE,
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.end = ORION_USB1_PHYS_BASE + SZ_4K,
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.flags = IORESOURCE_MEM,
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},
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{
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@ -177,8 +177,8 @@ static struct platform_device orion_ehci1 = {
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static struct resource orion_eth_shared_resources[] = {
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{
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.start = ORION_ETH_REG_BASE,
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.end = ORION_ETH_REG_BASE + 0xffff,
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.start = ORION_ETH_PHYS_BASE,
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.end = ORION_ETH_PHYS_BASE + 0xffff,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -227,8 +227,8 @@ static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
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static struct resource orion_i2c_resources[] = {
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{
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.name = "i2c base",
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.start = I2C_BASE,
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.end = I2C_BASE + 0x20 -1,
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.start = I2C_PHYS_BASE,
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.end = I2C_PHYS_BASE + 0x20 -1,
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.flags = IORESOURCE_MEM,
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},
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{
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@ -255,8 +255,8 @@ static struct platform_device orion_i2c = {
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static struct resource orion_sata_resources[] = {
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{
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.name = "sata base",
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.start = ORION_SATA_REG_BASE,
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.end = ORION_SATA_REG_BASE + 0x5000 - 1,
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.start = ORION_SATA_PHYS_BASE,
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.end = ORION_SATA_PHYS_BASE + 0x5000 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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@ -354,8 +354,8 @@ static void __init db88f5281_init(void)
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MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
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/* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
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.phys_io = ORION_REGS_BASE,
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.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc,
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.phys_io = ORION_REGS_PHYS_BASE,
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.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.init_machine = db88f5281_init,
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.map_io = orion_map_io,
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@ -259,8 +259,8 @@ static void __init dns323_init(void)
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*
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* Open a special address decode windows for the PCIE WA.
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*/
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orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
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orion_write(ORION_REGS_BASE | 0x20070,
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orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
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orion_write(ORION_REGS_VIRT_BASE | 0x20070,
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(0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
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/* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
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@ -312,8 +312,8 @@ static void __init dns323_init(void)
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/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
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MACHINE_START(DNS323, "D-Link DNS-323")
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/* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
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.phys_io = ORION_REGS_BASE,
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.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
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.phys_io = ORION_REGS_PHYS_BASE,
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.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
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.boot_params = 0x00000100,
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.init_machine = dns323_init,
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.map_io = orion_map_io,
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@ -192,8 +192,8 @@ static void __init kurobox_pro_init(void)
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/*
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* Open a special address decode windows for the PCIE WA.
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*/
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orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
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orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
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orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
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orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
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(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
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/*
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@ -224,8 +224,8 @@ static void __init kurobox_pro_init(void)
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MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
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/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
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.phys_io = ORION_REGS_BASE,
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.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
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.phys_io = ORION_REGS_PHYS_BASE,
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.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
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.boot_params = 0x00000100,
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.init_machine = kurobox_pro_init,
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.map_io = orion_map_io,
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@ -156,7 +156,7 @@ static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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orion_pcie_id(&dev, &rev);
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if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
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/* extended register space */
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pcie_addr = ORION_PCIE_WA_BASE;
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pcie_addr = ORION_PCIE_WA_VIRT_BASE;
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pcie_addr |= PCIE_CONF_BUS(bus->number) |
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PCIE_CONF_DEV(PCI_SLOT(devfn)) |
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PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
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@ -241,7 +241,7 @@ static int orion_pcie_setup(struct pci_sys_data *sys)
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*/
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res[0].name = "PCI-EX I/O Space";
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res[0].flags = IORESOURCE_IO;
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res[0].start = ORION_PCIE_IO_REMAP;
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res[0].start = ORION_PCIE_IO_BUS_BASE;
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res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
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if (request_resource(&ioport_resource, &res[0]))
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panic("Request PCIE IO resource failed\n");
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@ -252,7 +252,7 @@ static int orion_pcie_setup(struct pci_sys_data *sys)
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*/
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res[1].name = "PCI-EX Memory Space";
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res[1].flags = IORESOURCE_MEM;
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res[1].start = ORION_PCIE_MEM_BASE;
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res[1].start = ORION_PCIE_MEM_PHYS_BASE;
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res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
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if (request_resource(&iomem_resource, &res[1]))
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panic("Request PCIE Memory resource failed\n");
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@ -477,7 +477,7 @@ static int orion_pci_setup(struct pci_sys_data *sys)
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*/
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res[0].name = "PCI I/O Space";
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res[0].flags = IORESOURCE_IO;
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res[0].start = ORION_PCI_IO_REMAP;
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res[0].start = ORION_PCI_IO_BUS_BASE;
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res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
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if (request_resource(&ioport_resource, &res[0]))
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panic("Request PCI IO resource failed\n");
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@ -488,7 +488,7 @@ static int orion_pci_setup(struct pci_sys_data *sys)
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*/
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res[1].name = "PCI Memory Space";
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res[1].flags = IORESOURCE_MEM;
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res[1].start = ORION_PCI_MEM_BASE;
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res[1].start = ORION_PCI_MEM_PHYS_BASE;
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res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
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if (request_resource(&iomem_resource, &res[1]))
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panic("Request PCI Memory resource failed\n");
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@ -263,8 +263,8 @@ static void __init rd88f5182_init(void)
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/*
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* Open a special address decode windows for the PCIE WA.
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*/
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orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
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orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
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orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
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orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
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(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
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/*
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@ -305,8 +305,8 @@ static void __init rd88f5182_init(void)
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MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
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/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
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.phys_io = ORION_REGS_BASE,
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.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
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.phys_io = ORION_REGS_PHYS_BASE,
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.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
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.boot_params = 0x00000100,
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.init_machine = rd88f5182_init,
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.map_io = orion_map_io,
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@ -244,7 +244,7 @@ static struct platform_device *qnap_ts209_devices[] __initdata = {
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* QNAP TS-[12]09 specific power off method via UART1-attached PIC
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*/
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#define UART1_REG(x) (UART1_BASE + ((UART_##x) << 2))
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#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
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static void qnap_ts209_power_off(void)
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{
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@ -282,8 +282,8 @@ static void __init qnap_ts209_init(void)
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/*
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* Open a special address decode windows for the PCIE WA.
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*/
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orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
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orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
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orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
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orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
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(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
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/*
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@ -325,8 +325,8 @@ static void __init qnap_ts209_init(void)
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MACHINE_START(TS209, "QNAP TS-109/TS-209")
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/* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
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.phys_io = ORION_REGS_BASE,
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.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
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.phys_io = ORION_REGS_PHYS_BASE,
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.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
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.boot_params = 0x00000100,
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.init_machine = qnap_ts209_init,
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.map_io = orion_map_io,
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@ -8,9 +8,14 @@
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* published by the Free Software Foundation.
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*/
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#include <asm/arch/orion.h>
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.macro addruart,rx
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mov \rx, #0xf1000000
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orr \rx, \rx, #0x00012000
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mrc p15, 0, \rx, c1, c0
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tst \rx, #1 @ MMU enabled?
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ldreq \rx, =ORION_REGS_PHYS_BASE
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ldrne \rx, =ORION_REGS_VIRT_BASE
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orr \rx, \rx, #0x00012000
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.endm
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#define UART_SHIFT 2
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@ -3,8 +3,8 @@
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*
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* Low-level IRQ helper macros for Orion platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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@ -4,7 +4,6 @@
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_ARCH_HARDWARE_H__
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@ -12,13 +11,11 @@
|
|||
|
||||
#include "orion.h"
|
||||
|
||||
#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE
|
||||
#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
|
||||
#define pcibios_assign_all_busses() 1
|
||||
|
||||
#define pcibios_assign_all_busses() 1
|
||||
#define PCIBIOS_MIN_IO 0x00001000
|
||||
#define PCIBIOS_MIN_MEM 0x01000000
|
||||
#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE
|
||||
|
||||
#define PCIBIOS_MIN_IO 0x1000
|
||||
#define PCIBIOS_MIN_MEM 0x01000000
|
||||
#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
|
||||
|
||||
#endif /* _ASM_ARCH_HARDWARE_H */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,32 +14,40 @@
|
|||
#ifndef __ASM_ARCH_ORION_H__
|
||||
#define __ASM_ARCH_ORION_H__
|
||||
|
||||
/*******************************************************************************
|
||||
/*****************************************************************************
|
||||
* Orion Address Map
|
||||
* Use the same mapping (1:1 virtual:physical) of internal registers and
|
||||
* PCI system (PCI+PCIE) for all machines.
|
||||
* Each machine defines the rest of its mapping (e.g. device bus flashes)
|
||||
******************************************************************************/
|
||||
#define ORION_REGS_BASE 0xf1000000
|
||||
*
|
||||
* virt phys size
|
||||
* f0000000 f0000000 16M PCIe WA space (Orion-NAS only)
|
||||
* f1000000 f1000000 1M on-chip peripheral registers
|
||||
* f2000000 f2000000 1M PCIe I/O space
|
||||
* f2100000 f2100000 1M PCI I/O space
|
||||
****************************************************************************/
|
||||
#define ORION_REGS_PHYS_BASE 0xf1000000
|
||||
#define ORION_REGS_VIRT_BASE 0xf1000000
|
||||
#define ORION_REGS_SIZE SZ_1M
|
||||
|
||||
#define ORION_PCI_SYS_MEM_BASE 0xe0000000
|
||||
#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE
|
||||
#define ORION_PCIE_MEM_SIZE SZ_128M
|
||||
#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
|
||||
#define ORION_PCI_MEM_SIZE SZ_128M
|
||||
|
||||
#define ORION_PCI_SYS_IO_BASE 0xf2000000
|
||||
#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
|
||||
#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
|
||||
#define ORION_PCIE_IO_VIRT_BASE 0xf2000000
|
||||
#define ORION_PCIE_IO_BUS_BASE 0x00000000
|
||||
#define ORION_PCIE_IO_SIZE SZ_1M
|
||||
#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
|
||||
#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
|
||||
|
||||
#define ORION_PCI_IO_PHYS_BASE 0xf2100000
|
||||
#define ORION_PCI_IO_VIRT_BASE 0xf2100000
|
||||
#define ORION_PCI_IO_BUS_BASE 0x00100000
|
||||
#define ORION_PCI_IO_SIZE SZ_1M
|
||||
#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
|
||||
|
||||
/* Relevant only for Orion-NAS */
|
||||
#define ORION_PCIE_WA_BASE 0xf0000000
|
||||
#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
|
||||
#define ORION_PCIE_WA_VIRT_BASE 0xf0000000
|
||||
#define ORION_PCIE_WA_SIZE SZ_16M
|
||||
|
||||
#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000
|
||||
#define ORION_PCIE_MEM_SIZE SZ_128M
|
||||
|
||||
#define ORION_PCI_MEM_PHYS_BASE 0xe8000000
|
||||
#define ORION_PCI_MEM_SIZE SZ_128M
|
||||
|
||||
/*******************************************************************************
|
||||
* Supported Devices & Revisions
|
||||
******************************************************************************/
|
||||
|
|
@ -57,25 +65,42 @@
|
|||
/*******************************************************************************
|
||||
* Orion Registers Map
|
||||
******************************************************************************/
|
||||
#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000)
|
||||
#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000)
|
||||
#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000)
|
||||
#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000)
|
||||
#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000)
|
||||
#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000)
|
||||
#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000)
|
||||
#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000)
|
||||
#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000)
|
||||
#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000)
|
||||
#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x))
|
||||
|
||||
#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x))
|
||||
#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x))
|
||||
#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x))
|
||||
#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x))
|
||||
#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x))
|
||||
#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x))
|
||||
#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x))
|
||||
#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x))
|
||||
#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x))
|
||||
#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000)
|
||||
#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000)
|
||||
#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x))
|
||||
#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000)
|
||||
#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000)
|
||||
#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000)
|
||||
#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100)
|
||||
#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100)
|
||||
|
||||
#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
|
||||
#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
|
||||
|
||||
#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
|
||||
#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
|
||||
|
||||
#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000)
|
||||
#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x))
|
||||
|
||||
#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000)
|
||||
#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000)
|
||||
#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x))
|
||||
|
||||
#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000)
|
||||
#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000)
|
||||
#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x))
|
||||
|
||||
#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000)
|
||||
#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000)
|
||||
#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x))
|
||||
|
||||
#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000)
|
||||
#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000)
|
||||
#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x))
|
||||
|
||||
/*******************************************************************************
|
||||
* Device Bus Registers
|
||||
|
|
@ -100,9 +125,6 @@
|
|||
#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
|
||||
#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
|
||||
#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
|
||||
#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
|
||||
#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
|
||||
#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
|
||||
#define GPIO_MAX 32
|
||||
|
||||
/***************************************************************************
|
||||
|
|
|
|||
|
|
@ -10,8 +10,8 @@
|
|||
|
||||
#include <asm/arch/orion.h>
|
||||
|
||||
#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14))
|
||||
#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0))
|
||||
#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
|
||||
#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
|
||||
|
||||
#define LSR_THRE 0x20
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue