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drm/amd/pp: Delete is_smc_ram_running function on RV
1. There is a race condition when another ip also use same register pairs 2. check once at boot up by GetDriverIfVersion message is sufficient to check SMU health. so delete is_smc_ram_running check. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2 changed files with 0 additions and 28 deletions
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@ -47,34 +47,10 @@
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#define smnMP1_FIRMWARE_FLAGS 0x3010028
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bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr)
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{
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uint32_t mp1_fw_flags, reg;
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reg = soc15_get_register_offset(NBIF_HWID, 0,
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mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
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cgs_write_register(hwmgr->device, reg,
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(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
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reg = soc15_get_register_offset(NBIF_HWID, 0,
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mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
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mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
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if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
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return true;
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return false;
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}
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static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr)
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{
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uint32_t reg;
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if (!rv_is_smc_ram_running(hwmgr))
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return -EINVAL;
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reg = soc15_get_register_offset(MP1_HWID, 0,
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mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
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@ -89,9 +65,6 @@ int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
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{
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uint32_t reg;
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if (!rv_is_smc_ram_running(hwmgr))
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return -EINVAL;
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reg = soc15_get_register_offset(MP1_HWID, 0,
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mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
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cgs_write_register(hwmgr->device, reg, msg);
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@ -51,7 +51,6 @@ struct rv_smumgr {
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};
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int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
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bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr);
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int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id);
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int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
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