mvebu dt for v3.10 round 3
- mvebu PCIe DT support from round 2 (no pr was sent): - 64bit dts skeleton - mvebu devicebus additions - mvebu thermal nodes - mirabox gpio leds - orion5x xor and ehci - use mvsdio on guruplug dt -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQEcBAABAgAGBQJRbEtPAAoJEAi3KVZQDZAetzwH/1POQqgPrAbK/mOkQN11StLN Vd3I+QcA1x5GrYSwZ13HGCVoc/7ZXKBveNsKudH5lYXp1cRXQjKFz0DF4Pp+jo7S LII7u566sg7ZjaPWBSkyh3WA2HNK4lzAXwWa+DfrDDlwRNNVBkCGQ8MlP5d22NYF SRQLAyDo2czD0ARocoG8jLJ3tKXcxMAtfDzUSw29tsAky+IWp8eYD6xPvQusY4L1 5Wp/Y3Sjixg87Ktcj8u6fd8scvhoP+Y4gcsx/OOfYRxS/iE+ApwQKoHYnbL1xoZB PbRaXsitZJDMoXnSMfa2ZuW3IEfKML88a64tTR1jVhvYK+/wwEwa2v84PqAiOrY= =huPy -----END PGP SIGNATURE----- Merge tag 'dt-3.10-3' of git://git.infradead.org/users/jcooper/linux into next/dt From Jason Cooper: mvebu dt for v3.10 round 3 - mvebu PCIe DT support from round 2 (no pr was sent): - 64bit dts skeleton - mvebu devicebus additions - mvebu thermal nodes - mirabox gpio leds - orion5x xor and ehci - use mvsdio on guruplug dt * tag 'dt-3.10-3' of git://git.infradead.org/users/jcooper/linux: arm: mvebu: PCIe Device Tree informations for Armada XP GP arm: mvebu: PCIe Device Tree informations for Armada 370 DB arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox arm: mvebu: PCIe Device Tree informations for Armada XP DB arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4 arm: mvebu: add PCIe Device Tree informations for Armada XP arm: mvebu: add PCIe Device Tree informations for Armada 370 ARM: dts: Add a 64 bits version of the skeleton device tree ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board ARM: mvebu: Add support for NOR flash device on Armada XP-GP board ARM: mvebu: Add Device Bus support for Armada 370/XP SoC ARM: configs: Update mvebu defconfig for thermal ARM: mvebu: Add thermal support to Armada 370 device tree ARM: mvebu: Add thermal support to Armada XP device tree arm: mvebu: Add GPIO LEDs to Mirabox board arm: orion5x: enable xor for orion5x platform arm: orion5x: add ehci bindings to dtsi ARM: kirkwood: make use of DT mvsdio on guruplug board ARM: mvebu: Add button on Armada 370 Reference Design board
This commit is contained in:
Olof Johansson
commit
7fa7ed8e1c
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|
@ -94,5 +94,22 @@
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|||
spi-max-frequency = <50000000>;
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||||
};
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||||
};
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||||
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||||
pcie-controller {
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status = "okay";
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||||
/*
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||||
* The two PCIe units are accessible through
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||||
* both standard PCIe slots and mini-PCIe
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* slots on the board.
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||||
*/
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||||
pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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||||
};
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||||
pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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||||
};
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||||
};
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};
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||||
|
|
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@ -33,6 +33,43 @@
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clock-frequency = <600000000>;
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status = "okay";
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};
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pinctrl {
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pwr_led_pin: pwr-led-pin {
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marvell,pins = "mpp63";
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marvell,function = "gpo";
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};
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stat_led_pins: stat-led-pins {
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marvell,pins = "mpp64", "mpp65";
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marvell,function = "gpio";
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};
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};
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gpio_leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
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green_pwr_led {
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label = "mirabox:green:pwr";
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gpios = <&gpio1 31 1>;
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linux,default-trigger = "heartbeat";
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};
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blue_stat_led {
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label = "mirabox:blue:stat";
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gpios = <&gpio2 0 1>;
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linux,default-trigger = "cpu0";
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};
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green_stat_led {
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label = "mirabox:green:stat";
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gpios = <&gpio2 1 1>;
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default-state = "off";
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};
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};
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mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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@ -81,5 +118,21 @@
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reg = <0x25>;
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};
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};
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pcie-controller {
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status = "okay";
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/* Internal mini-PCIe connector */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* Connected on the PCB to a USB 3.0 XHCI controller */
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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@ -73,4 +73,15 @@
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status = "okay";
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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button@1 {
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label = "Software Button";
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linux,code = <116>;
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gpios = <&gpio0 6 1>;
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};
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};
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};
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@ -181,6 +181,51 @@
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-bootcs@d0010400 {
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compatible = "marvell,mvebu-devbus";
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reg = <0xd0010400 0x8>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs0@d0010408 {
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compatible = "marvell,mvebu-devbus";
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reg = <0xd0010408 0x8>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs1@d0010410 {
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compatible = "marvell,mvebu-devbus";
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reg = <0xd0010410 0x8>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs2@d0010418 {
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compatible = "marvell,mvebu-devbus";
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reg = <0xd0010418 0x8>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs3@d0010420 {
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compatible = "marvell,mvebu-devbus";
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reg = <0xd0010420 0x8>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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||||
};
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};
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};
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|
|
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@ -153,5 +153,63 @@
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clocks = <&coreclk 0>;
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};
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thermal@d0018300 {
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compatible = "marvell,armada370-thermal";
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reg = <0xd0018300 0x4
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0xd0018304 0x4>;
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status = "okay";
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||||
};
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pcie-controller {
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compatible = "marvell,armada-370-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;
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reg-names = "pcie0.0", "pcie1.0";
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ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
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0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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};
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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||||
interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 62>;
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||||
marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 9>;
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status = "disabled";
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||||
};
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||||
};
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||||
};
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||||
};
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||||
|
|
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|||
|
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@ -121,5 +121,38 @@
|
|||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
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||||
status = "okay";
|
||||
|
||||
/*
|
||||
* All 6 slots are physically present as
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
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||||
status = "okay";
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};
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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pcie@3,0 {
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/* Port 0, Lane 2 */
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status = "okay";
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};
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pcie@4,0 {
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/* Port 0, Lane 3 */
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status = "okay";
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};
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pcie@9,0 {
|
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/* Port 2, Lane 0 */
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status = "okay";
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};
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pcie@10,0 {
|
||||
/* Port 3, Lane 0 */
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status = "okay";
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||||
};
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||||
};
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||||
};
|
||||
};
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||||
|
|
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|||
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@ -109,5 +109,55 @@
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spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
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devbus-bootcs@d0010400 {
|
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status = "okay";
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ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
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||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
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devbus,bus-width = <8>;
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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/* NOR 16 MiB */
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nor@0 {
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compatible = "cfi-flash";
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reg = <0 0x1000000>;
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bank-width = <2>;
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};
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||||
};
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||||
|
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pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* The 3 slots are physically present as
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@9,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@10,0 {
|
||||
/* Port 3, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -76,5 +76,109 @@
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#interrupts-cells = <2>;
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||||
interrupts = <87>, <88>, <89>;
|
||||
};
|
||||
|
||||
/*
|
||||
* MV78230 has 2 PCIe units Gen2.0: One unit can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -96,5 +96,127 @@
|
|||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* MV78260 has 3 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0082000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -111,5 +111,193 @@
|
|||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* MV78460 has 4 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. Two units are
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -139,5 +139,43 @@
|
|||
usb@d0051000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
devbus-bootcs@d0010400 {
|
||||
status = "okay";
|
||||
ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <8>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 128 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -151,5 +151,11 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
thermal@d00182b0 {
|
||||
compatible = "marvell,armadaxp-thermal";
|
||||
reg = <0xd00182b0 0x4
|
||||
0xd00184d0 0x4>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -69,6 +69,10 @@
|
|||
status = "okay";
|
||||
nr-ports = <1>;
|
||||
};
|
||||
|
||||
mvsdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
|
|
|
|||
|
|
@ -69,6 +69,20 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
ehci@50000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x50000 0x1000>;
|
||||
interrupts = <17>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci@a0000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0xa0000 0x1000>;
|
||||
interrupts = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata@80000 {
|
||||
compatible = "marvell,orion-sata";
|
||||
reg = <0x80000 0x5000>;
|
||||
|
|
@ -86,6 +100,25 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <30>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <31>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
crypto@90000 {
|
||||
compatible = "marvell,orion-crypto";
|
||||
reg = <0x90000 0x10000>,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Skeleton device tree in the 64 bits version; the bare minimum
|
||||
* needed to boot; just include and add a compatible value. The
|
||||
* bootloader will typically populate the memory node.
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
chosen { };
|
||||
aliases { };
|
||||
memory { device_type = "memory"; reg = <0 0>; };
|
||||
};
|
||||
|
|
@ -46,9 +46,16 @@ CONFIG_I2C_MV64XXX=y
|
|||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_ARMADA_THERMAL=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
|
@ -65,6 +72,8 @@ CONFIG_RTC_DRV_S35390A=y
|
|||
CONFIG_RTC_DRV_MV=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_MV_XOR=y
|
||||
CONFIG_MEMORY=y
|
||||
CONFIG_MVEBU_DEVBUS=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
|
|
|
|||
|
|
@ -13,7 +13,6 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/mv643xx_eth.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_data/mmc-mvsdio.h>
|
||||
#include "common.h"
|
||||
|
||||
static struct mv643xx_eth_platform_data guruplug_ge00_data = {
|
||||
|
|
@ -24,10 +23,6 @@ static struct mv643xx_eth_platform_data guruplug_ge01_data = {
|
|||
.phy_addr = MV643XX_ETH_PHY_ADDR(1),
|
||||
};
|
||||
|
||||
static struct mvsdio_platform_data guruplug_mvsdio_data = {
|
||||
/* unfortunately the CD signal has not been connected */
|
||||
};
|
||||
|
||||
void __init guruplug_dt_init(void)
|
||||
{
|
||||
/*
|
||||
|
|
@ -35,5 +30,4 @@ void __init guruplug_dt_init(void)
|
|||
*/
|
||||
kirkwood_ge00_init(&guruplug_ge00_data);
|
||||
kirkwood_ge01_init(&guruplug_ge01_data);
|
||||
kirkwood_sdio_init(&guruplug_mvsdio_data);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue