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staging: comedi: amplc_dio200: split into ISA, PCI and common
Split the "amplc_dio200" comedi driver module into separate driver modules for ISA and PCI boards with a common module for the shared code. Keep the old name "amplc_dio200" for the ISA board driver as the module may be modprobed with this name by a script. (If the script uses insmod it will need modifying to load the "amplc_dio200_common" module first.) Use the module name "amplc_dio200_pci" for the PCI board driver. On most systems this will be auto-loaded. Use the module name "amplc_dio200_common" for the module containing the shared code. This is normally loaded as a dependency of the other two modules. "amplc_dio200_common" exports the following functions: * `amplc_dio200_common_attach()`: this is basically the old `dio200_common_attach()` from the combined driver module. It is called from the driver-specific attach or auto-attach routines. * `amplc_dio200_common_detach()`: this is most of the old `dio200_detach()`. It is called from the driver-specific detach routine. * `amplc_dio200_set_enhance()`: this is a new function called during initialization of PCIe cards to enable "enhanced" mode. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
8d68837786
commit
7ff7e4c2c4
5 changed files with 1947 additions and 1684 deletions
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@ -12,6 +12,7 @@ obj-$(CONFIG_COMEDI_SKEL) += skel.o
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# Comedi ISA drivers
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obj-$(CONFIG_COMEDI_ACL7225B) += acl7225b.o
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obj-$(CONFIG_COMEDI_AMPLC_DIO200_ISA) += amplc_dio200.o
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obj-$(CONFIG_COMEDI_PCL711) += pcl711.o
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obj-$(CONFIG_COMEDI_PCL724) += pcl724.o
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obj-$(CONFIG_COMEDI_PCL725) += pcl725.o
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@ -77,7 +78,7 @@ obj-$(CONFIG_COMEDI_ADV_PCI1710) += adv_pci1710.o
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obj-$(CONFIG_COMEDI_ADV_PCI1723) += adv_pci1723.o
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obj-$(CONFIG_COMEDI_ADV_PCI1724) += adv_pci1724.o
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obj-$(CONFIG_COMEDI_ADV_PCI_DIO) += adv_pci_dio.o
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obj-$(CONFIG_COMEDI_AMPLC_DIO200) += amplc_dio200.o
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obj-$(CONFIG_COMEDI_AMPLC_DIO200_PCI) += amplc_dio200_pci.o
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obj-$(CONFIG_COMEDI_AMPLC_PC236) += amplc_pc236.o
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obj-$(CONFIG_COMEDI_AMPLC_PC263) += amplc_pc263.o
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obj-$(CONFIG_COMEDI_AMPLC_PCI224) += amplc_pci224.o
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@ -134,5 +135,6 @@ obj-$(CONFIG_COMEDI_NI_TIOCMD) += ni_tiocmd.o
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obj-$(CONFIG_COMEDI_NI_LABPC) += ni_labpc.o
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obj-$(CONFIG_COMEDI_8255) += 8255.o
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obj-$(CONFIG_COMEDI_AMPLC_DIO200) += amplc_dio200_common.o
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obj-$(CONFIG_COMEDI_DAS08) += das08.o
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obj-$(CONFIG_COMEDI_FC) += comedi_fc.o
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File diff suppressed because it is too large
Load diff
95
drivers/staging/comedi/drivers/amplc_dio200.h
Normal file
95
drivers/staging/comedi/drivers/amplc_dio200.h
Normal file
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@ -0,0 +1,95 @@
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/*
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comedi/drivers/amplc_dio.h
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Header for amplc_dio200.c, amplc_dio200_common.c and
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amplc_dio200_pci.c.
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Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
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COMEDI - Linux Control and Measurement Device Interface
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Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef AMPLC_DIO200_H_INCLUDED
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#define AMPLC_DIO200_H_INCLUDED
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/* 200 series register area sizes */
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#define DIO200_IO_SIZE 0x20
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#define DIO200_PCIE_IO_SIZE 0x4000
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/*
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* Register region.
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*/
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enum dio200_regtype { no_regtype = 0, io_regtype, mmio_regtype };
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struct dio200_region {
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union {
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unsigned long iobase; /* I/O base address */
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unsigned char __iomem *membase; /* mapped MMIO base address */
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} u;
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enum dio200_regtype regtype;
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};
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/*
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* Subdevice types.
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*/
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enum dio200_sdtype { sd_none, sd_intr, sd_8255, sd_8254, sd_timer };
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#define DIO200_MAX_SUBDEVS 8
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#define DIO200_MAX_ISNS 6
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/*
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* Board descriptions.
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*/
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struct dio200_layout {
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unsigned short n_subdevs; /* number of subdevices */
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unsigned char sdtype[DIO200_MAX_SUBDEVS]; /* enum dio200_sdtype */
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unsigned char sdinfo[DIO200_MAX_SUBDEVS]; /* depends on sdtype */
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bool has_int_sce:1; /* has interrupt enable/status reg */
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bool has_clk_gat_sce:1; /* has clock/gate selection registers */
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bool has_enhancements:1; /* has enhanced features */
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};
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enum dio200_bustype { isa_bustype, pci_bustype };
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struct dio200_board {
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const char *name;
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struct dio200_layout layout;
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enum dio200_bustype bustype;
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unsigned char mainbar;
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unsigned char mainshift;
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unsigned int mainsize;
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};
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/*
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* Comedi device private data.
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*/
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struct dio200_private {
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struct dio200_region io; /* Register region */
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int intr_sd;
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};
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int amplc_dio200_common_attach(struct comedi_device *dev, unsigned int irq,
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unsigned long req_irq_flags);
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void amplc_dio200_common_detach(struct comedi_device *dev);
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/* Used by initialization of PCIe boards. */
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void amplc_dio200_set_enhance(struct comedi_device *dev, unsigned char val);
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#endif
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1320
drivers/staging/comedi/drivers/amplc_dio200_common.c
Normal file
1320
drivers/staging/comedi/drivers/amplc_dio200_common.c
Normal file
File diff suppressed because it is too large
Load diff
492
drivers/staging/comedi/drivers/amplc_dio200_pci.c
Normal file
492
drivers/staging/comedi/drivers/amplc_dio200_pci.c
Normal file
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@ -0,0 +1,492 @@
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/* comedi/drivers/amplc_dio200_pci.c
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Driver for Amplicon PCI215, PCI272, PCIe215, PCIe236, PCIe296.
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Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
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COMEDI - Linux Control and Measurement Device Interface
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Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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* Driver: amplc_dio200_pci
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* Description: Amplicon 200 Series PCI Digital I/O
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* Author: Ian Abbott <abbotti@mev.co.uk>
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* Devices: [Amplicon] PCI215 (amplc_dio200_pci), PCIe215, PCIe236,
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* PCI272, PCIe296
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* Updated: Mon, 18 Mar 2013 15:03:50 +0000
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* Status: works
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*
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* Configuration options:
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* none
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*
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* Manual configuration of PCI(e) cards is not supported; they are configured
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* automatically.
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*
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* SUBDEVICES
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*
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* PCI215 PCIe215 PCIe236
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* ------------- ------------- -------------
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* Subdevices 5 8 8
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* 0 PPI-X PPI-X PPI-X
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* 1 PPI-Y UNUSED UNUSED
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* 2 CTR-Z1 PPI-Y UNUSED
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* 3 CTR-Z2 UNUSED UNUSED
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* 4 INTERRUPT CTR-Z1 CTR-Z1
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* 5 CTR-Z2 CTR-Z2
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* 6 TIMER TIMER
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* 7 INTERRUPT INTERRUPT
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*
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*
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* PCI272 PCIe296
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* ------------- -------------
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* Subdevices 4 8
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* 0 PPI-X PPI-X1
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* 1 PPI-Y PPI-X2
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* 2 PPI-Z PPI-Y1
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* 3 INTERRUPT PPI-Y2
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* 4 CTR-Z1
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* 5 CTR-Z2
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* 6 TIMER
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* 7 INTERRUPT
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*
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* Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels
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* are configurable as inputs or outputs in four groups:
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*
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* Port A - channels 0 to 7
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* Port B - channels 8 to 15
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* Port CL - channels 16 to 19
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* Port CH - channels 20 to 23
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*
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* Only mode 0 of the 8255 chips is supported.
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*
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* Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
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* channel is configured individually with INSN_CONFIG instructions. The
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* specific type of configuration instruction is specified in data[0].
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* Some configuration instructions expect an additional parameter in
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* data[1]; others return a value in data[1]. The following configuration
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* instructions are supported:
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*
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* INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
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* BCD/binary setting specified in data[1].
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*
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* INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the
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* counter channel into data[1].
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*
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* INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
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* specified in data[1] (this is a hardware-specific value). Not
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* supported on PC214E. For the other boards, valid clock sources are
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* 0 to 7 as follows:
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*
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* 0. CLK n, the counter channel's dedicated CLK input from the SK1
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* connector. (N.B. for other values, the counter channel's CLKn
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* pin on the SK1 connector is an output!)
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* 1. Internal 10 MHz clock.
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* 2. Internal 1 MHz clock.
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* 3. Internal 100 kHz clock.
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* 4. Internal 10 kHz clock.
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* 5. Internal 1 kHz clock.
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* 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
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* 7. Ext Clock, the counter chip's dedicated Ext Clock input from
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* the SK1 connector. This pin is shared by all three counter
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* channels on the chip.
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*
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* For the PCIe boards, clock sources in the range 0 to 31 are allowed
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* and the following additional clock sources are defined:
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*
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* 8. HIGH logic level.
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* 9. LOW logic level.
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* 10. "Pattern present" signal.
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* 11. Internal 20 MHz clock.
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*
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* INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
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* clock source in data[1]. For internal clock sources, data[2] is set
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* to the period in ns.
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*
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* INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
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* specified in data[2] (this is a hardware-specific value). Not
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* supported on PC214E. For the other boards, valid gate sources are 0
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* to 7 as follows:
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*
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* 0. VCC (internal +5V d.c.), i.e. gate permanently enabled.
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* 1. GND (internal 0V d.c.), i.e. gate permanently disabled.
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* 2. GAT n, the counter channel's dedicated GAT input from the SK1
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* connector. (N.B. for other values, the counter channel's GATn
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* pin on the SK1 connector is an output!)
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* 3. /OUT n-2, the inverted output of counter channel n-2 (see note
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* 2 below).
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* 4. Reserved.
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* 5. Reserved.
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* 6. Reserved.
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* 7. Reserved.
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*
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* For the PCIe boards, gate sources in the range 0 to 31 are allowed;
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* the following additional clock sources and clock sources 6 and 7 are
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* (re)defined:
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*
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* 6. /GAT n, negated version of the counter channel's dedicated
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* GAT input (negated version of gate source 2).
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* 7. OUT n-2, the non-inverted output of counter channel n-2
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* (negated version of gate source 3).
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* 8. "Pattern present" signal, HIGH while pattern present.
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* 9. "Pattern occurred" latched signal, latches HIGH when pattern
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* occurs.
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* 10. "Pattern gone away" latched signal, latches LOW when pattern
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* goes away after it occurred.
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* 11. Negated "pattern present" signal, LOW while pattern present
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* (negated version of gate source 8).
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* 12. Negated "pattern occurred" latched signal, latches LOW when
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* pattern occurs (negated version of gate source 9).
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* 13. Negated "pattern gone away" latched signal, latches LOW when
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* pattern goes away after it occurred (negated version of gate
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* source 10).
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*
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* INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
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* source in data[2].
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*
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* Clock and gate interconnection notes:
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*
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* 1. Clock source OUT n-1 is the output of the preceding channel on the
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* same counter subdevice if n > 0, or the output of channel 2 on the
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* preceding counter subdevice (see note 3) if n = 0.
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*
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* 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
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* same counter subdevice if n = 2, or the inverted output of channel n+1
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* on the preceding counter subdevice (see note 3) if n < 2.
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*
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* 3. The counter subdevices are connected in a ring, so the highest
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* counter subdevice precedes the lowest.
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*
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* The 'TIMER' subdevice is a free-running 32-bit timer subdevice.
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*
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* The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
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* digital inputs come from the interrupt status register. The number of
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* channels matches the number of interrupt sources. The PC214E does not
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* have an interrupt status register; see notes on 'INTERRUPT SOURCES'
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* below.
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*
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* INTERRUPT SOURCES
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*
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* PCI215 PCIe215 PCIe236
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* ------------- ------------- -------------
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* Sources 6 6 6
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* 0 PPI-X-C0 PPI-X-C0 PPI-X-C0
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* 1 PPI-X-C3 PPI-X-C3 PPI-X-C3
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* 2 PPI-Y-C0 PPI-Y-C0 unused
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* 3 PPI-Y-C3 PPI-Y-C3 unused
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* 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1
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* 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1
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*
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* PCI272 PCIe296
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* ------------- -------------
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* Sources 6 6
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* 0 PPI-X-C0 PPI-X1-C0
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* 1 PPI-X-C3 PPI-X1-C3
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* 2 PPI-Y-C0 PPI-Y1-C0
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* 3 PPI-Y-C3 PPI-Y1-C3
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* 4 PPI-Z-C0 CTR-Z1-OUT1
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* 5 PPI-Z-C3 CTR-Z2-OUT1
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*
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* When an interrupt source is enabled in the interrupt source enable
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* register, a rising edge on the source signal latches the corresponding
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* bit to 1 in the interrupt status register.
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*
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* When the interrupt status register value as a whole (actually, just the
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* 6 least significant bits) goes from zero to non-zero, the board will
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* generate an interrupt. The interrupt will remain asserted until the
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* interrupt status register is cleared to zero. To clear a bit to zero in
|
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* the interrupt status register, the corresponding interrupt source must
|
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* be disabled in the interrupt source enable register (there is no
|
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* separate interrupt clear register).
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*
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* COMMANDS
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*
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* The driver supports a read streaming acquisition command on the
|
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* 'INTERRUPT' subdevice. The channel list selects the interrupt sources
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* to be enabled. All channels will be sampled together (convert_src ==
|
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* TRIG_NOW). The scan begins a short time after the hardware interrupt
|
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* occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
|
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* scan_begin_arg == 0). The value read from the interrupt status register
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* is packed into a short value, one bit per requested channel, in the
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* order they appear in the channel list.
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*/
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include "../comedidev.h"
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|
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#include "amplc_dio200.h"
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/* PCI IDs */
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#define PCI_DEVICE_ID_AMPLICON_PCI272 0x000a
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#define PCI_DEVICE_ID_AMPLICON_PCI215 0x000b
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#define PCI_DEVICE_ID_AMPLICON_PCIE236 0x0011
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#define PCI_DEVICE_ID_AMPLICON_PCIE215 0x0012
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#define PCI_DEVICE_ID_AMPLICON_PCIE296 0x0014
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/*
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* Board descriptions.
|
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*/
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enum dio200_pci_model {
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pci215_model,
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pci272_model,
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pcie215_model,
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pcie236_model,
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pcie296_model
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};
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static const struct dio200_board dio200_pci_boards[] = {
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[pci215_model] {
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.name = "pci215",
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.bustype = pci_bustype,
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.mainbar = 2,
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.mainsize = DIO200_IO_SIZE,
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.layout = {
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.n_subdevs = 5,
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||||
.sdtype = {sd_8255, sd_8255, sd_8254, sd_8254, sd_intr},
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.sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F},
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.has_int_sce = true,
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.has_clk_gat_sce = true,
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},
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},
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[pci272_model] {
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.name = "pci272",
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.bustype = pci_bustype,
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.mainbar = 2,
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.mainsize = DIO200_IO_SIZE,
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.layout = {
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.n_subdevs = 4,
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.sdtype = {sd_8255, sd_8255, sd_8255, sd_intr},
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||||
.sdinfo = {0x00, 0x08, 0x10, 0x3F},
|
||||
.has_int_sce = true,
|
||||
},
|
||||
},
|
||||
[pcie215_model] {
|
||||
.name = "pcie215",
|
||||
.bustype = pci_bustype,
|
||||
.mainbar = 1,
|
||||
.mainshift = 3,
|
||||
.mainsize = DIO200_PCIE_IO_SIZE,
|
||||
.layout = {
|
||||
.n_subdevs = 8,
|
||||
.sdtype = {sd_8255, sd_none, sd_8255, sd_none,
|
||||
sd_8254, sd_8254, sd_timer, sd_intr},
|
||||
.sdinfo = {0x00, 0x00, 0x08, 0x00,
|
||||
0x10, 0x14, 0x00, 0x3F},
|
||||
.has_int_sce = true,
|
||||
.has_clk_gat_sce = true,
|
||||
.has_enhancements = true,
|
||||
},
|
||||
},
|
||||
[pcie236_model] {
|
||||
.name = "pcie236",
|
||||
.bustype = pci_bustype,
|
||||
.mainbar = 1,
|
||||
.mainshift = 3,
|
||||
.mainsize = DIO200_PCIE_IO_SIZE,
|
||||
.layout = {
|
||||
.n_subdevs = 8,
|
||||
.sdtype = {sd_8255, sd_none, sd_none, sd_none,
|
||||
sd_8254, sd_8254, sd_timer, sd_intr},
|
||||
.sdinfo = {0x00, 0x00, 0x00, 0x00,
|
||||
0x10, 0x14, 0x00, 0x3F},
|
||||
.has_int_sce = true,
|
||||
.has_clk_gat_sce = true,
|
||||
.has_enhancements = true,
|
||||
},
|
||||
},
|
||||
[pcie296_model] {
|
||||
.name = "pcie296",
|
||||
.bustype = pci_bustype,
|
||||
.mainbar = 1,
|
||||
.mainshift = 3,
|
||||
.mainsize = DIO200_PCIE_IO_SIZE,
|
||||
.layout = {
|
||||
.n_subdevs = 8,
|
||||
.sdtype = {sd_8255, sd_8255, sd_8255, sd_8255,
|
||||
sd_8254, sd_8254, sd_timer, sd_intr},
|
||||
.sdinfo = {0x00, 0x04, 0x08, 0x0C,
|
||||
0x10, 0x14, 0x00, 0x3F},
|
||||
.has_int_sce = true,
|
||||
.has_clk_gat_sce = true,
|
||||
.has_enhancements = true,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* This function does some special set-up for the PCIe boards
|
||||
* PCIe215, PCIe236, PCIe296.
|
||||
*/
|
||||
static int dio200_pcie_board_setup(struct comedi_device *dev)
|
||||
{
|
||||
struct pci_dev *pcidev = comedi_to_pci_dev(dev);
|
||||
void __iomem *brbase;
|
||||
resource_size_t brlen;
|
||||
|
||||
/*
|
||||
* The board uses Altera Cyclone IV with PCI-Express hard IP.
|
||||
* The FPGA configuration has the PCI-Express Avalon-MM Bridge
|
||||
* Control registers in PCI BAR 0, offset 0, and the length of
|
||||
* these registers is 0x4000.
|
||||
*
|
||||
* We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt
|
||||
* Enable" register at offset 0x50 to allow generation of PCIe
|
||||
* interrupts when RXmlrq_i is asserted in the SOPC Builder system.
|
||||
*/
|
||||
brlen = pci_resource_len(pcidev, 0);
|
||||
if (brlen < 0x4000 ||
|
||||
!(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM)) {
|
||||
dev_err(dev->class_dev, "error! bad PCI region!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
brbase = ioremap_nocache(pci_resource_start(pcidev, 0), brlen);
|
||||
if (!brbase) {
|
||||
dev_err(dev->class_dev, "error! failed to map registers!\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
writel(0x80, brbase + 0x50);
|
||||
iounmap(brbase);
|
||||
/* Enable "enhanced" features of board. */
|
||||
amplc_dio200_set_enhance(dev, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dio200_pci_auto_attach(struct comedi_device *dev,
|
||||
unsigned long context_model)
|
||||
{
|
||||
struct pci_dev *pci_dev = comedi_to_pci_dev(dev);
|
||||
const struct dio200_board *thisboard = NULL;
|
||||
struct dio200_private *devpriv;
|
||||
resource_size_t base, len;
|
||||
unsigned int bar;
|
||||
int ret;
|
||||
|
||||
if (context_model < ARRAY_SIZE(dio200_pci_boards))
|
||||
thisboard = &dio200_pci_boards[context_model];
|
||||
if (!thisboard)
|
||||
return -EINVAL;
|
||||
dev->board_ptr = thisboard;
|
||||
dev->board_name = thisboard->name;
|
||||
|
||||
dev_info(dev->class_dev, "%s: attach pci %s (%s)\n",
|
||||
dev->driver->driver_name, pci_name(pci_dev), dev->board_name);
|
||||
|
||||
devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
|
||||
if (!devpriv)
|
||||
return -ENOMEM;
|
||||
dev->private = devpriv;
|
||||
|
||||
ret = comedi_pci_enable(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
bar = thisboard->mainbar;
|
||||
base = pci_resource_start(pci_dev, bar);
|
||||
len = pci_resource_len(pci_dev, bar);
|
||||
if (len < thisboard->mainsize) {
|
||||
dev_err(dev->class_dev, "error! PCI region size too small!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
if (pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) {
|
||||
devpriv->io.u.membase = ioremap_nocache(base, len);
|
||||
if (!devpriv->io.u.membase) {
|
||||
dev_err(dev->class_dev,
|
||||
"error! cannot remap registers\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
devpriv->io.regtype = mmio_regtype;
|
||||
} else {
|
||||
devpriv->io.u.iobase = (unsigned long)base;
|
||||
devpriv->io.regtype = io_regtype;
|
||||
}
|
||||
switch (context_model) {
|
||||
case pcie215_model:
|
||||
case pcie236_model:
|
||||
case pcie296_model:
|
||||
ret = dio200_pcie_board_setup(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return amplc_dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED);
|
||||
}
|
||||
|
||||
static void dio200_pci_detach(struct comedi_device *dev)
|
||||
{
|
||||
const struct dio200_board *thisboard = comedi_board(dev);
|
||||
struct dio200_private *devpriv = dev->private;
|
||||
|
||||
if (!thisboard || !devpriv)
|
||||
return;
|
||||
amplc_dio200_common_detach(dev);
|
||||
if (devpriv->io.regtype == mmio_regtype)
|
||||
iounmap(devpriv->io.u.membase);
|
||||
comedi_pci_disable(dev);
|
||||
}
|
||||
|
||||
static struct comedi_driver dio200_pci_comedi_driver = {
|
||||
.driver_name = "amplc_dio200_pci",
|
||||
.module = THIS_MODULE,
|
||||
.auto_attach = dio200_pci_auto_attach,
|
||||
.detach = dio200_pci_detach,
|
||||
};
|
||||
|
||||
static DEFINE_PCI_DEVICE_TABLE(dio200_pci_table) = {
|
||||
{
|
||||
PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI215),
|
||||
pci215_model
|
||||
}, {
|
||||
PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI272),
|
||||
pci272_model
|
||||
}, {
|
||||
PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE236),
|
||||
pcie236_model
|
||||
}, {
|
||||
PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE215),
|
||||
pcie215_model
|
||||
}, {
|
||||
PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE296),
|
||||
pcie296_model
|
||||
},
|
||||
{0}
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, dio200_pci_table);
|
||||
|
||||
static int dio200_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
{
|
||||
return comedi_pci_auto_config(dev, &dio200_pci_comedi_driver,
|
||||
id->driver_data);
|
||||
}
|
||||
|
||||
static struct pci_driver dio200_pci_pci_driver = {
|
||||
.name = "amplc_dio200_pci",
|
||||
.id_table = dio200_pci_table,
|
||||
.probe = dio200_pci_probe,
|
||||
.remove = comedi_pci_auto_unconfig,
|
||||
};
|
||||
module_comedi_pci_driver(dio200_pci_comedi_driver, dio200_pci_pci_driver);
|
||||
|
||||
MODULE_AUTHOR("Comedi http://www.comedi.org");
|
||||
MODULE_DESCRIPTION("Comedi driver for Amplicon 200 Series PCI(e) DIO boards");
|
||||
MODULE_LICENSE("GPL");
|
Loading…
Reference in a new issue