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thermal: samsung: Remove support for Exynos5440
The Exynos5440 is not actively developed, there are no development boards available and probably there are no real products with it. Remove wide-tree support for Exynos5440. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> [b.zolnierkie: ported over driver changes] Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
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2e7db3eceb
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8014220d48
2 changed files with 4 additions and 171 deletions
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@ -12,7 +12,6 @@
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"samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
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Exynos5420 (Must pass triminfo base and triminfo clock)
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"samsung,exynos5433-tmu"
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"samsung,exynos5440-tmu"
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"samsung,exynos7-tmu"
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- interrupt-parent : The phandle for the interrupt controller
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- reg : Address range of the thermal registers. For soc's which has multiple
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@ -68,18 +67,7 @@ Example 1):
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#thermal-sensor-cells = <0>;
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};
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Example 2):
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tmuctrl_0: tmuctrl@160118 {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x160118 0x230>, <0x160368 0x10>;
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interrupts = <0 58 0>;
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clocks = <&clock 21>;
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clock-names = "tmu_apbif";
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#thermal-sensor-cells = <0>;
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};
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Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
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Example 2): (In case of Exynos5420 "with misplaced TRIMINFO register")
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tmu_cpu2: tmu@10068000 {
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compatible = "samsung,exynos5420-tmu-ext-triminfo";
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reg = <0x10068000 0x100>, <0x1006c000 0x4>;
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@ -126,28 +126,6 @@
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#define EXYNOS5433_G3D_BASE 0x10070000
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/*exynos5440 specific registers*/
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#define EXYNOS5440_TMU_S0_7_TRIM 0x000
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#define EXYNOS5440_TMU_S0_7_CTRL 0x020
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#define EXYNOS5440_TMU_S0_7_DEBUG 0x040
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#define EXYNOS5440_TMU_S0_7_TEMP 0x0f0
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#define EXYNOS5440_TMU_S0_7_TH0 0x110
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#define EXYNOS5440_TMU_S0_7_TH1 0x130
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#define EXYNOS5440_TMU_S0_7_TH2 0x150
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#define EXYNOS5440_TMU_S0_7_IRQEN 0x210
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#define EXYNOS5440_TMU_S0_7_IRQ 0x230
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/* exynos5440 common registers */
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#define EXYNOS5440_TMU_IRQ_STATUS 0x000
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#define EXYNOS5440_TMU_PMIN 0x004
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#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
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#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
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#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
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#define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
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#define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
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#define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
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#define EXYNOS5440_EFUSE_SWAP_OFFSET 8
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/* Exynos7 specific registers */
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#define EXYNOS7_THD_TEMP_RISE7_6 0x50
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#define EXYNOS7_THD_TEMP_FALL7_6 0x60
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@ -184,7 +162,6 @@ enum soc_type {
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SOC_ARCH_EXYNOS5420,
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SOC_ARCH_EXYNOS5420_TRIMINFO,
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SOC_ARCH_EXYNOS5433,
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SOC_ARCH_EXYNOS5440,
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SOC_ARCH_EXYNOS7,
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};
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@ -619,57 +596,6 @@ static int exynos5433_tmu_initialize(struct platform_device *pdev)
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return ret;
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}
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static int exynos5440_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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unsigned int trim_info = 0, con, rising_threshold;
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int threshold_code;
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int crit_temp = 0;
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/*
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* For exynos5440 soc triminfo value is swapped between TMU0 and
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* TMU2, so the below logic is needed.
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*/
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switch (data->id) {
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case 0:
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trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
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EXYNOS5440_TMU_S0_7_TRIM);
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break;
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case 1:
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trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
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break;
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case 2:
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trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +
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EXYNOS5440_TMU_S0_7_TRIM);
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}
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sanitize_temp_error(data, trim_info);
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/* Write temperature code for rising and falling threshold */
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rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
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rising_threshold = get_th_reg(data, rising_threshold, false);
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writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
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writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
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data->tmu_clear_irqs(data);
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/* if last threshold limit is also present */
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if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) {
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threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
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/* 5th level to be assigned in th2 reg */
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rising_threshold =
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threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
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writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
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con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
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con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
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writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
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}
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/* Clear the PMIN in the common TMU register */
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if (!data->id)
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writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
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return 0;
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}
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static int exynos7_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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@ -820,35 +746,6 @@ static void exynos5433_tmu_control(struct platform_device *pdev, bool on)
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writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
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}
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static void exynos5440_tmu_control(struct platform_device *pdev, bool on)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct thermal_zone_device *tz = data->tzd;
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unsigned int con, interrupt_en;
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con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));
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if (on) {
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con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
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interrupt_en =
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(of_thermal_is_trip_valid(tz, 3)
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<< EXYNOS5440_TMU_INTEN_RISE3_SHIFT) |
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(of_thermal_is_trip_valid(tz, 2)
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<< EXYNOS5440_TMU_INTEN_RISE2_SHIFT) |
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(of_thermal_is_trip_valid(tz, 1)
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<< EXYNOS5440_TMU_INTEN_RISE1_SHIFT) |
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(of_thermal_is_trip_valid(tz, 0)
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<< EXYNOS5440_TMU_INTEN_RISE0_SHIFT);
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interrupt_en |=
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interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;
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} else {
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con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
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interrupt_en = 0; /* Disable all interrupts */
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}
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writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);
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writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
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}
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static void exynos7_tmu_control(struct platform_device *pdev, bool on)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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@ -920,10 +817,8 @@ static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
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if (temp) {
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temp /= MCELSIUS;
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if (data->soc != SOC_ARCH_EXYNOS5440) {
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val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
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val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
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}
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val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
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val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
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if (data->soc == SOC_ARCH_EXYNOS7) {
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val &= ~(EXYNOS7_EMUL_DATA_MASK <<
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EXYNOS7_EMUL_DATA_SHIFT);
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@ -964,16 +859,6 @@ static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
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writel(val, data->base + emul_con);
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}
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static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data,
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int temp)
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{
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unsigned int val;
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val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG);
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val = get_emul_con_reg(data, val, temp);
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writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG);
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}
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static int exynos_tmu_set_emulation(void *drv_data, int temp)
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{
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struct exynos_tmu_data *data = drv_data;
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@ -996,7 +881,6 @@ static int exynos_tmu_set_emulation(void *drv_data, int temp)
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}
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#else
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#define exynos4412_tmu_set_emulation NULL
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#define exynos5440_tmu_set_emulation NULL
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static int exynos_tmu_set_emulation(void *drv_data, int temp)
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{ return -EINVAL; }
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#endif /* CONFIG_THERMAL_EMULATION */
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@ -1014,11 +898,6 @@ static int exynos4412_tmu_read(struct exynos_tmu_data *data)
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return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
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}
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static int exynos5440_tmu_read(struct exynos_tmu_data *data)
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{
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return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP);
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}
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static int exynos7_tmu_read(struct exynos_tmu_data *data)
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{
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return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) &
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@ -1029,16 +908,9 @@ static void exynos_tmu_work(struct work_struct *work)
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{
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struct exynos_tmu_data *data = container_of(work,
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struct exynos_tmu_data, irq_work);
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unsigned int val_type;
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if (!IS_ERR(data->clk_sec))
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clk_enable(data->clk_sec);
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/* Find which sensor generated this interrupt */
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if (data->soc == SOC_ARCH_EXYNOS5440) {
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val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
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if (!((val_type >> data->id) & 0x1))
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goto out;
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}
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if (!IS_ERR(data->clk_sec))
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clk_disable(data->clk_sec);
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@ -1051,7 +923,6 @@ static void exynos_tmu_work(struct work_struct *work)
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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out:
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enable_irq(data->irq);
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}
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@ -1086,15 +957,6 @@ static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
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writel(val_irq, data->base + tmu_intclear);
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}
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static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data)
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{
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unsigned int val_irq;
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val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ);
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/* clear the interrupts */
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writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ);
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}
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static irqreturn_t exynos_tmu_irq(int irq, void *id)
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{
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struct exynos_tmu_data *data = id;
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@ -1130,9 +992,6 @@ static const struct of_device_id exynos_tmu_match[] = {
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}, {
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.compatible = "samsung,exynos5433-tmu",
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.data = (const void *)SOC_ARCH_EXYNOS5433,
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}, {
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.compatible = "samsung,exynos5440-tmu",
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.data = (const void *)SOC_ARCH_EXYNOS5440,
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}, {
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.compatible = "samsung,exynos7-tmu",
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.data = (const void *)SOC_ARCH_EXYNOS7,
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@ -1223,19 +1082,6 @@ static int exynos_map_dt_data(struct platform_device *pdev)
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data->min_efuse_value = 40;
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data->max_efuse_value = 150;
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break;
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case SOC_ARCH_EXYNOS5440:
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data->tmu_initialize = exynos5440_tmu_initialize;
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data->tmu_control = exynos5440_tmu_control;
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data->tmu_read = exynos5440_tmu_read;
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data->tmu_set_emulation = exynos5440_tmu_set_emulation;
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data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
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data->ntrip = 4;
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data->gain = 5;
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data->reference_voltage = 16;
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data->efuse_value = 0x5d2d;
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data->min_efuse_value = 16;
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data->max_efuse_value = 76;
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break;
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case SOC_ARCH_EXYNOS7:
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data->tmu_initialize = exynos7_tmu_initialize;
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data->tmu_control = exynos7_tmu_control;
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@ -1260,8 +1106,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
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* Check if the TMU shares some registers and then try to map the
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* memory of common registers.
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*/
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if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO &&
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data->soc != SOC_ARCH_EXYNOS5440)
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if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)
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return 0;
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if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
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