mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 11:19:37 +00:00
Renesas driver updates for v5.10 (take two)
- Add core support for the R-Car V3U (R8A779A0) SoC, including System
Controller (SYSC) and Reset (RST) support,
- Various Kconfig cleanups.
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Merge tag 'renesas-drivers-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers
Renesas driver updates for v5.10 (take two)
- Add core support for the R-Car V3U (R8A779A0) SoC, including System
Controller (SYSC) and Reset (RST) support,
- Various Kconfig cleanups.
* tag 'renesas-drivers-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: r8a779a0-sysc: Add r8a779a0 support
soc: renesas: rcar-rst: Add support for R-Car V3U
soc: renesas: Identify R-Car V3U
soc: renesas: Sort driver description title
soc: renesas: Use ARM32/ARM64 for menu description
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779a0 SYSC power domain definitions
Link: https://lore.kernel.org/r/20200918124800.15555-4-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
802b26b3c2
7 changed files with 768 additions and 183 deletions
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@ -49,78 +49,18 @@ if ARM && ARCH_RENESAS
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|||
#comment "Renesas ARM SoCs System Type"
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config ARCH_EMEV2
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bool "SoC Platform support for Emma Mobile EV2"
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bool "ARM32 Platform support for Emma Mobile EV2"
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select HAVE_ARM_SCU if SMP
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select SYS_SUPPORTS_EM_STI
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config ARCH_R7S72100
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bool "SoC Platform support for RZ/A1H"
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select ARM_ERRATA_754322
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select PM
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select PM_GENERIC_DOMAINS
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select RENESAS_OSTM
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select RENESAS_RZA1_IRQC
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select SYS_SUPPORTS_SH_MTU2
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config ARCH_R7S9210
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bool "SoC Platform support for RZ/A2"
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select PM
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select PM_GENERIC_DOMAINS
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select RENESAS_OSTM
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select RENESAS_RZA1_IRQC
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config ARCH_R8A73A4
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bool "SoC Platform support for R-Mobile APE6"
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select ARCH_RMOBILE
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select ARM_ERRATA_798181 if SMP
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select ARM_ERRATA_814220
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select HAVE_ARM_ARCH_TIMER
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select RENESAS_IRQC
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config ARCH_R8A7740
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bool "SoC Platform support for R-Mobile A1"
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select ARCH_RMOBILE
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select ARM_ERRATA_754322
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select RENESAS_INTC_IRQPIN
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config ARCH_R8A7742
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bool "SoC Platform support for RZ/G1H"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_798181 if SMP
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select ARM_ERRATA_814220
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select SYSC_R8A7742
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config ARCH_R8A7743
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bool "SoC Platform support for RZ/G1M"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_798181 if SMP
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select SYSC_R8A7743
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config ARCH_R8A7744
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bool "SoC Platform support for RZ/G1N"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_798181 if SMP
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select SYSC_R8A7743
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config ARCH_R8A7745
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bool "SoC Platform support for RZ/G1E"
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config ARCH_R8A7794
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bool "ARM32 Platform support for R-Car E2"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_814220
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select SYSC_R8A7745
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config ARCH_R8A77470
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bool "SoC Platform support for RZ/G1C"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_814220
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select SYSC_R8A77470
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config ARCH_R8A7778
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bool "SoC Platform support for R-Car M1A"
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select ARCH_RCAR_GEN1
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select ARM_ERRATA_754322
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select SYSC_R8A7794
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config ARCH_R8A7779
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bool "SoC Platform support for R-Car H1"
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bool "ARM32 Platform support for R-Car H1"
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select ARCH_RCAR_GEN1
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select ARM_ERRATA_754322
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select ARM_GLOBAL_TIMER
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@ -129,46 +69,106 @@ config ARCH_R8A7779
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select SYSC_R8A7779
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config ARCH_R8A7790
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bool "SoC Platform support for R-Car H2"
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bool "ARM32 Platform support for R-Car H2"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_798181 if SMP
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select ARM_ERRATA_814220
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select I2C
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select SYSC_R8A7790
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config ARCH_R8A7778
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bool "ARM32 Platform support for R-Car M1A"
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select ARCH_RCAR_GEN1
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select ARM_ERRATA_754322
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config ARCH_R8A7793
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bool "ARM32 Platform support for R-Car M2-N"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_798181 if SMP
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select I2C
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select SYSC_R8A7791
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config ARCH_R8A7791
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bool "SoC Platform support for R-Car M2-W"
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bool "ARM32 Platform support for R-Car M2-W"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_798181 if SMP
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select I2C
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select SYSC_R8A7791
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config ARCH_R8A7792
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bool "SoC Platform support for R-Car V2H"
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bool "ARM32 Platform support for R-Car V2H"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_798181 if SMP
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select SYSC_R8A7792
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config ARCH_R8A7793
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bool "SoC Platform support for R-Car M2-N"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_798181 if SMP
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select I2C
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select SYSC_R8A7791
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config ARCH_R8A7740
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bool "ARM32 Platform support for R-Mobile A1"
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select ARCH_RMOBILE
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select ARM_ERRATA_754322
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select RENESAS_INTC_IRQPIN
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config ARCH_R8A7794
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bool "SoC Platform support for R-Car E2"
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config ARCH_R8A73A4
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bool "ARM32 Platform support for R-Mobile APE6"
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select ARCH_RMOBILE
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select ARM_ERRATA_798181 if SMP
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select ARM_ERRATA_814220
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select HAVE_ARM_ARCH_TIMER
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select RENESAS_IRQC
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config ARCH_R7S72100
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bool "ARM32 Platform support for RZ/A1H"
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select ARM_ERRATA_754322
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select PM
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select PM_GENERIC_DOMAINS
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select RENESAS_OSTM
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select RENESAS_RZA1_IRQC
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select SYS_SUPPORTS_SH_MTU2
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config ARCH_R7S9210
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bool "ARM32 Platform support for RZ/A2"
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select PM
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select PM_GENERIC_DOMAINS
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select RENESAS_OSTM
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select RENESAS_RZA1_IRQC
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config ARCH_R8A77470
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bool "ARM32 Platform support for RZ/G1C"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_814220
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select SYSC_R8A7794
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select SYSC_R8A77470
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config ARCH_R8A7745
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bool "ARM32 Platform support for RZ/G1E"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_814220
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select SYSC_R8A7745
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config ARCH_R8A7742
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bool "ARM32 Platform support for RZ/G1H"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_798181 if SMP
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select ARM_ERRATA_814220
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select SYSC_R8A7742
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config ARCH_R8A7743
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bool "ARM32 Platform support for RZ/G1M"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_798181 if SMP
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select SYSC_R8A7743
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config ARCH_R8A7744
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bool "ARM32 Platform support for RZ/G1N"
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select ARCH_RCAR_GEN2
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select ARM_ERRATA_798181 if SMP
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select SYSC_R8A7743
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config ARCH_R9A06G032
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bool "SoC Platform support for RZ/N1D"
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bool "ARM32 Platform support for RZ/N1D"
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select ARCH_RZN1
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select ARM_ERRATA_814220
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config ARCH_SH73A0
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bool "SoC Platform support for SH-Mobile AG5"
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bool "ARM32 Platform support for SH-Mobile AG5"
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select ARCH_RMOBILE
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select ARM_ERRATA_754322
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select ARM_GLOBAL_TIMER
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@ -180,131 +180,123 @@ endif # ARM
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if ARM64
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config ARCH_R8A774A1
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bool "SoC Platform support for RZ/G2M"
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config ARCH_R8A77995
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bool "ARM64 Platform support for R-Car D3"
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select ARCH_RCAR_GEN3
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select SYSC_R8A774A1
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select SYSC_R8A77995
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help
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This enables support for the Renesas RZ/G2M SoC.
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This enables support for the Renesas R-Car D3 SoC.
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config ARCH_R8A774B1
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bool "SoC Platform support for RZ/G2N"
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config ARCH_R8A77990
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bool "ARM64 Platform support for R-Car E3"
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select ARCH_RCAR_GEN3
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select SYSC_R8A774B1
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select SYSC_R8A77990
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help
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This enables support for the Renesas RZ/G2N SoC.
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config ARCH_R8A774C0
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bool "SoC Platform support for RZ/G2E"
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select ARCH_RCAR_GEN3
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select SYSC_R8A774C0
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help
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This enables support for the Renesas RZ/G2E SoC.
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config ARCH_R8A774E1
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bool "SoC Platform support for RZ/G2H"
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select ARCH_RCAR_GEN3
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select SYSC_R8A774E1
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help
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This enables support for the Renesas RZ/G2H SoC.
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This enables support for the Renesas R-Car E3 SoC.
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config ARCH_R8A77950
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bool "SoC Platform support for R-Car H3 ES1.x"
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bool "ARM64 Platform support for R-Car H3 ES1.x"
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select ARCH_RCAR_GEN3
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select SYSC_R8A7795
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help
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This enables support for the Renesas R-Car H3 SoC (revision 1.x).
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config ARCH_R8A77951
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bool "SoC Platform support for R-Car H3 ES2.0+"
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bool "ARM64 Platform support for R-Car H3 ES2.0+"
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select ARCH_RCAR_GEN3
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select SYSC_R8A7795
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help
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This enables support for the Renesas R-Car H3 SoC (revisions 2.0 and
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later).
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config ARCH_R8A77965
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bool "ARM64 Platform support for R-Car M3-N"
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select ARCH_RCAR_GEN3
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select SYSC_R8A77965
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help
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This enables support for the Renesas R-Car M3-N SoC.
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config ARCH_R8A77960
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bool "SoC Platform support for R-Car M3-W"
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bool "ARM64 Platform support for R-Car M3-W"
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select ARCH_RCAR_GEN3
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select SYSC_R8A77960
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help
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This enables support for the Renesas R-Car M3-W SoC.
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config ARCH_R8A77961
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bool "SoC Platform support for R-Car M3-W+"
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bool "ARM64 Platform support for R-Car M3-W+"
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select ARCH_RCAR_GEN3
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select SYSC_R8A77961
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help
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This enables support for the Renesas R-Car M3-W+ SoC.
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config ARCH_R8A77965
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bool "SoC Platform support for R-Car M3-N"
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select ARCH_RCAR_GEN3
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select SYSC_R8A77965
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help
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This enables support for the Renesas R-Car M3-N SoC.
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config ARCH_R8A77970
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bool "SoC Platform support for R-Car V3M"
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select ARCH_RCAR_GEN3
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select SYSC_R8A77970
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help
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This enables support for the Renesas R-Car V3M SoC.
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config ARCH_R8A77980
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bool "SoC Platform support for R-Car V3H"
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bool "ARM64 Platform support for R-Car V3H"
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select ARCH_RCAR_GEN3
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select SYSC_R8A77980
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help
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This enables support for the Renesas R-Car V3H SoC.
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config ARCH_R8A77990
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bool "SoC Platform support for R-Car E3"
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config ARCH_R8A77970
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bool "ARM64 Platform support for R-Car V3M"
|
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select ARCH_RCAR_GEN3
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select SYSC_R8A77990
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select SYSC_R8A77970
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||||
help
|
||||
This enables support for the Renesas R-Car E3 SoC.
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||||
This enables support for the Renesas R-Car V3M SoC.
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config ARCH_R8A77995
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bool "SoC Platform support for R-Car D3"
|
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config ARCH_R8A779A0
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bool "ARM64 Platform support for R-Car V3U"
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select ARCH_RCAR_GEN3
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select SYSC_R8A77995
|
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select SYSC_R8A779A0
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||||
help
|
||||
This enables support for the Renesas R-Car D3 SoC.
|
||||
This enables support for the Renesas R-Car V3U SoC.
|
||||
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||||
config ARCH_R8A774C0
|
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bool "ARM64 Platform support for RZ/G2E"
|
||||
select ARCH_RCAR_GEN3
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select SYSC_R8A774C0
|
||||
help
|
||||
This enables support for the Renesas RZ/G2E SoC.
|
||||
|
||||
config ARCH_R8A774E1
|
||||
bool "ARM64 Platform support for RZ/G2H"
|
||||
select ARCH_RCAR_GEN3
|
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select SYSC_R8A774E1
|
||||
help
|
||||
This enables support for the Renesas RZ/G2H SoC.
|
||||
|
||||
config ARCH_R8A774A1
|
||||
bool "ARM64 Platform support for RZ/G2M"
|
||||
select ARCH_RCAR_GEN3
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select SYSC_R8A774A1
|
||||
help
|
||||
This enables support for the Renesas RZ/G2M SoC.
|
||||
|
||||
config ARCH_R8A774B1
|
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bool "ARM64 Platform support for RZ/G2N"
|
||||
select ARCH_RCAR_GEN3
|
||||
select SYSC_R8A774B1
|
||||
help
|
||||
This enables support for the Renesas RZ/G2N SoC.
|
||||
|
||||
endif # ARM64
|
||||
|
||||
# SoC
|
||||
config SYSC_R8A7742
|
||||
bool "System Controller support for RZ/G1H" if COMPILE_TEST
|
||||
config RST_RCAR
|
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bool "Reset Controller support for R-Car" if COMPILE_TEST
|
||||
|
||||
config SYSC_RCAR
|
||||
bool "System Controller support for R-Car" if COMPILE_TEST
|
||||
|
||||
config SYSC_R8A77995
|
||||
bool "System Controller support for R-Car D3" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A7743
|
||||
bool "System Controller support for RZ/G1M" if COMPILE_TEST
|
||||
config SYSC_R8A7794
|
||||
bool "System Controller support for R-Car E2" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A7745
|
||||
bool "System Controller support for RZ/G1E" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A77470
|
||||
bool "System Controller support for RZ/G1C" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A774A1
|
||||
bool "System Controller support for RZ/G2M" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A774B1
|
||||
bool "System Controller support for RZ/G2N" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A774C0
|
||||
bool "System Controller support for RZ/G2E" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A774E1
|
||||
bool "System Controller support for RZ/G2H" if COMPILE_TEST
|
||||
config SYSC_R8A77990
|
||||
bool "System Controller support for R-Car E3" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A7779
|
||||
|
|
@ -315,20 +307,16 @@ config SYSC_R8A7790
|
|||
bool "System Controller support for R-Car H2" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A7795
|
||||
bool "System Controller support for R-Car H3" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A7791
|
||||
bool "System Controller support for R-Car M2-W/N" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A7792
|
||||
bool "System Controller support for R-Car V2H" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A7794
|
||||
bool "System Controller support for R-Car E2" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A7795
|
||||
bool "System Controller support for R-Car H3" if COMPILE_TEST
|
||||
config SYSC_R8A77965
|
||||
bool "System Controller support for R-Car M3-N" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A77960
|
||||
|
|
@ -339,34 +327,54 @@ config SYSC_R8A77961
|
|||
bool "System Controller support for R-Car M3-W+" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A77965
|
||||
bool "System Controller support for R-Car M3-N" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A77970
|
||||
bool "System Controller support for R-Car V3M" if COMPILE_TEST
|
||||
config SYSC_R8A7792
|
||||
bool "System Controller support for R-Car V2H" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A77980
|
||||
bool "System Controller support for R-Car V3H" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A77990
|
||||
bool "System Controller support for R-Car E3" if COMPILE_TEST
|
||||
config SYSC_R8A77970
|
||||
bool "System Controller support for R-Car V3M" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A77995
|
||||
bool "System Controller support for R-Car D3" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
# Family
|
||||
config RST_RCAR
|
||||
bool "Reset Controller support for R-Car" if COMPILE_TEST
|
||||
|
||||
config SYSC_RCAR
|
||||
bool "System Controller support for R-Car" if COMPILE_TEST
|
||||
config SYSC_R8A779A0
|
||||
bool "System Controller support for R-Car V3U" if COMPILE_TEST
|
||||
|
||||
config SYSC_RMOBILE
|
||||
bool "System Controller support for R-Mobile" if COMPILE_TEST
|
||||
|
||||
config SYSC_R8A77470
|
||||
bool "System Controller support for RZ/G1C" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A7745
|
||||
bool "System Controller support for RZ/G1E" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A7742
|
||||
bool "System Controller support for RZ/G1H" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A7743
|
||||
bool "System Controller support for RZ/G1M" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A774C0
|
||||
bool "System Controller support for RZ/G2E" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A774E1
|
||||
bool "System Controller support for RZ/G2H" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A774A1
|
||||
bool "System Controller support for RZ/G2M" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
config SYSC_R8A774B1
|
||||
bool "System Controller support for RZ/G2N" if COMPILE_TEST
|
||||
select SYSC_RCAR
|
||||
|
||||
endif # SOC_RENESAS
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ obj-$(CONFIG_SYSC_R8A77970) += r8a77970-sysc.o
|
|||
obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o
|
||||
obj-$(CONFIG_SYSC_R8A77990) += r8a77990-sysc.o
|
||||
obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o
|
||||
obj-$(CONFIG_SYSC_R8A779A0) += r8a779a0-sysc.o
|
||||
ifdef CONFIG_SMP
|
||||
obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o
|
||||
endif
|
||||
|
|
|
|||
448
drivers/soc/renesas/r8a779a0-sysc.c
Normal file
448
drivers/soc/renesas/r8a779a0-sysc.c
Normal file
|
|
@ -0,0 +1,448 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R-Car V3U System Controller
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/clk/renesas.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <dt-bindings/power/r8a779a0-sysc.h>
|
||||
|
||||
/*
|
||||
* Power Domain flags
|
||||
*/
|
||||
#define PD_CPU BIT(0) /* Area contains main CPU core */
|
||||
#define PD_SCU BIT(1) /* Area contains SCU and L2 cache */
|
||||
#define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */
|
||||
|
||||
#define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR */
|
||||
#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
|
||||
|
||||
/*
|
||||
* Description of a Power Area
|
||||
*/
|
||||
struct r8a779a0_sysc_area {
|
||||
const char *name;
|
||||
u8 pdr; /* PDRn */
|
||||
int parent; /* -1 if none */
|
||||
unsigned int flags; /* See PD_* */
|
||||
};
|
||||
|
||||
/*
|
||||
* SoC-specific Power Area Description
|
||||
*/
|
||||
struct r8a779a0_sysc_info {
|
||||
const struct r8a779a0_sysc_area *areas;
|
||||
unsigned int num_areas;
|
||||
};
|
||||
|
||||
static struct r8a779a0_sysc_area r8a779a0_areas[] __initdata = {
|
||||
{ "always-on", R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
|
||||
{ "a3e0", R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU },
|
||||
{ "a3e1", R8A779A0_PD_A3E1, R8A779A0_PD_ALWAYS_ON, PD_SCU },
|
||||
{ "a2e0d0", R8A779A0_PD_A2E0D0, R8A779A0_PD_A3E0, PD_SCU },
|
||||
{ "a2e0d1", R8A779A0_PD_A2E0D1, R8A779A0_PD_A3E0, PD_SCU },
|
||||
{ "a2e1d0", R8A779A0_PD_A2E1D0, R8A779A0_PD_A3E1, PD_SCU },
|
||||
{ "a2e1d1", R8A779A0_PD_A2E1D1, R8A779A0_PD_A3E1, PD_SCU },
|
||||
{ "a1e0d0c0", R8A779A0_PD_A1E0D0C0, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
|
||||
{ "a1e0d0c1", R8A779A0_PD_A1E0D0C1, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
|
||||
{ "a1e0d1c0", R8A779A0_PD_A1E0D1C0, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
|
||||
{ "a1e0d1c1", R8A779A0_PD_A1E0D1C1, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
|
||||
{ "a1e1d0c0", R8A779A0_PD_A1E1D0C0, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
|
||||
{ "a1e1d0c1", R8A779A0_PD_A1E1D0C1, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
|
||||
{ "a1e1d1c0", R8A779A0_PD_A1E1D1C0, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
|
||||
{ "a1e1d1c1", R8A779A0_PD_A1E1D1C1, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
|
||||
{ "3dg-a", R8A779A0_PD_3DG_A, R8A779A0_PD_ALWAYS_ON },
|
||||
{ "3dg-b", R8A779A0_PD_3DG_B, R8A779A0_PD_3DG_A },
|
||||
{ "a3vip0", R8A779A0_PD_A3VIP0, R8A779A0_PD_ALWAYS_ON },
|
||||
{ "a3vip1", R8A779A0_PD_A3VIP1, R8A779A0_PD_ALWAYS_ON },
|
||||
{ "a3vip3", R8A779A0_PD_A3VIP3, R8A779A0_PD_ALWAYS_ON },
|
||||
{ "a3vip2", R8A779A0_PD_A3VIP2, R8A779A0_PD_ALWAYS_ON },
|
||||
{ "a3isp01", R8A779A0_PD_A3ISP01, R8A779A0_PD_ALWAYS_ON },
|
||||
{ "a3isp23", R8A779A0_PD_A3ISP23, R8A779A0_PD_ALWAYS_ON },
|
||||
{ "a3ir", R8A779A0_PD_A3IR, R8A779A0_PD_ALWAYS_ON },
|
||||
{ "a2cn0", R8A779A0_PD_A2CN0, R8A779A0_PD_A3IR },
|
||||
{ "a2imp01", R8A779A0_PD_A2IMP01, R8A779A0_PD_A3IR },
|
||||
{ "a2dp0", R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
|
||||
{ "a2cv0", R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
|
||||
{ "a2cv1", R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
|
||||
{ "a2cv4", R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
|
||||
{ "a2cv6", R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
|
||||
{ "a2cn2", R8A779A0_PD_A2CN2, R8A779A0_PD_A3IR },
|
||||
{ "a2imp23", R8A779A0_PD_A2IMP23, R8A779A0_PD_A3IR },
|
||||
{ "a2dp1", R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
|
||||
{ "a2cv2", R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
|
||||
{ "a2cv3", R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
|
||||
{ "a2cv5", R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
|
||||
{ "a2cv7", R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
|
||||
{ "a2cn1", R8A779A0_PD_A2CN1, R8A779A0_PD_A3IR },
|
||||
{ "a1cnn0", R8A779A0_PD_A1CNN0, R8A779A0_PD_A2CN0 },
|
||||
{ "a1cnn2", R8A779A0_PD_A1CNN2, R8A779A0_PD_A2CN2 },
|
||||
{ "a1dsp0", R8A779A0_PD_A1DSP0, R8A779A0_PD_A2CN2 },
|
||||
{ "a1cnn1", R8A779A0_PD_A1CNN1, R8A779A0_PD_A2CN1 },
|
||||
{ "a1dsp1", R8A779A0_PD_A1DSP1, R8A779A0_PD_A2CN1 },
|
||||
};
|
||||
|
||||
static const struct r8a779a0_sysc_info r8a779a0_sysc_info __initconst = {
|
||||
.areas = r8a779a0_areas,
|
||||
.num_areas = ARRAY_SIZE(r8a779a0_areas),
|
||||
};
|
||||
|
||||
/* SYSC Common */
|
||||
#define SYSCSR 0x000 /* SYSC Status Register */
|
||||
#define SYSCPONSR(x) (0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */
|
||||
#define SYSCPOFFSR(x) (0x808 + ((x) * 0x4)) /* Power-OFF Status Register */
|
||||
#define SYSCISCR(x) (0x810 + ((x) * 0x4)) /* Interrupt Status/Clear Register */
|
||||
#define SYSCIER(x) (0x820 + ((x) * 0x4)) /* Interrupt Enable Register */
|
||||
#define SYSCIMR(x) (0x830 + ((x) * 0x4)) /* Interrupt Mask Register */
|
||||
|
||||
/* Power Domain Registers */
|
||||
#define PDRSR(n) (0x1000 + ((n) * 0x40))
|
||||
#define PDRONCR(n) (0x1004 + ((n) * 0x40))
|
||||
#define PDROFFCR(n) (0x1008 + ((n) * 0x40))
|
||||
#define PDRESR(n) (0x100C + ((n) * 0x40))
|
||||
|
||||
/* PWRON/PWROFF */
|
||||
#define PWRON_PWROFF BIT(0) /* Power-ON/OFF request */
|
||||
|
||||
/* PDRESR */
|
||||
#define PDRESR_ERR BIT(0)
|
||||
|
||||
/* PDRSR */
|
||||
#define PDRSR_OFF BIT(0) /* Power-OFF state */
|
||||
#define PDRSR_ON BIT(4) /* Power-ON state */
|
||||
#define PDRSR_OFF_STATE BIT(8) /* Processing Power-OFF sequence */
|
||||
#define PDRSR_ON_STATE BIT(12) /* Processing Power-ON sequence */
|
||||
|
||||
#define SYSCSR_BUSY GENMASK(1, 0) /* All bit sets is not busy */
|
||||
|
||||
#define SYSCSR_TIMEOUT 10000
|
||||
#define SYSCSR_DELAY_US 10
|
||||
|
||||
#define PDRESR_RETRIES 1000
|
||||
#define PDRESR_DELAY_US 10
|
||||
|
||||
#define SYSCISR_TIMEOUT 10000
|
||||
#define SYSCISR_DELAY_US 10
|
||||
|
||||
#define NUM_DOMAINS_EACH_REG BITS_PER_TYPE(u32)
|
||||
|
||||
static void __iomem *r8a779a0_sysc_base;
|
||||
static DEFINE_SPINLOCK(r8a779a0_sysc_lock); /* SMP CPUs + I/O devices */
|
||||
|
||||
static int r8a779a0_sysc_pwr_on_off(u8 pdr, bool on)
|
||||
{
|
||||
unsigned int reg_offs;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
if (on)
|
||||
reg_offs = PDRONCR(pdr);
|
||||
else
|
||||
reg_offs = PDROFFCR(pdr);
|
||||
|
||||
/* Wait until SYSC is ready to accept a power request */
|
||||
ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCSR, val,
|
||||
(val & SYSCSR_BUSY) == SYSCSR_BUSY,
|
||||
SYSCSR_DELAY_US, SYSCSR_TIMEOUT);
|
||||
if (ret < 0)
|
||||
return -EAGAIN;
|
||||
|
||||
/* Submit power shutoff or power resume request */
|
||||
iowrite32(PWRON_PWROFF, r8a779a0_sysc_base + reg_offs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask)
|
||||
{
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
iowrite32(isr_mask, r8a779a0_sysc_base + SYSCISCR(reg_idx));
|
||||
|
||||
ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx),
|
||||
val, !(val & isr_mask),
|
||||
SYSCISR_DELAY_US, SYSCISR_TIMEOUT);
|
||||
if (ret < 0) {
|
||||
pr_err("\n %s : Can not clear IRQ flags in SYSCISCR", __func__);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int r8a779a0_sysc_power(u8 pdr, bool on)
|
||||
{
|
||||
unsigned int isr_mask;
|
||||
unsigned int reg_idx, bit_idx;
|
||||
unsigned int status;
|
||||
unsigned long flags;
|
||||
int ret = 0;
|
||||
u32 val;
|
||||
int k;
|
||||
|
||||
spin_lock_irqsave(&r8a779a0_sysc_lock, flags);
|
||||
|
||||
reg_idx = pdr / NUM_DOMAINS_EACH_REG;
|
||||
bit_idx = pdr % NUM_DOMAINS_EACH_REG;
|
||||
|
||||
isr_mask = BIT(bit_idx);
|
||||
|
||||
/*
|
||||
* The interrupt source needs to be enabled, but masked, to prevent the
|
||||
* CPU from receiving it.
|
||||
*/
|
||||
iowrite32(ioread32(r8a779a0_sysc_base + SYSCIER(reg_idx)) | isr_mask,
|
||||
r8a779a0_sysc_base + SYSCIER(reg_idx));
|
||||
iowrite32(ioread32(r8a779a0_sysc_base + SYSCIMR(reg_idx)) | isr_mask,
|
||||
r8a779a0_sysc_base + SYSCIMR(reg_idx));
|
||||
|
||||
ret = clear_irq_flags(reg_idx, isr_mask);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/* Submit power shutoff or resume request until it was accepted */
|
||||
for (k = 0; k < PDRESR_RETRIES; k++) {
|
||||
ret = r8a779a0_sysc_pwr_on_off(pdr, on);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
status = ioread32(r8a779a0_sysc_base + PDRESR(pdr));
|
||||
if (!(status & PDRESR_ERR))
|
||||
break;
|
||||
|
||||
udelay(PDRESR_DELAY_US);
|
||||
}
|
||||
|
||||
if (k == PDRESR_RETRIES) {
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Wait until the power shutoff or resume request has completed * */
|
||||
ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx),
|
||||
val, (val & isr_mask),
|
||||
SYSCISR_DELAY_US, SYSCISR_TIMEOUT);
|
||||
if (ret < 0) {
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Clear interrupt flags */
|
||||
ret = clear_irq_flags(reg_idx, isr_mask);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
out:
|
||||
spin_unlock_irqrestore(&r8a779a0_sysc_lock, flags);
|
||||
|
||||
pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
|
||||
pdr, ioread32(r8a779a0_sysc_base + SYSCISCR(reg_idx)), ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static bool r8a779a0_sysc_power_is_off(u8 pdr)
|
||||
{
|
||||
unsigned int st;
|
||||
|
||||
st = ioread32(r8a779a0_sysc_base + PDRSR(pdr));
|
||||
|
||||
if (st & PDRSR_OFF)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
struct r8a779a0_sysc_pd {
|
||||
struct generic_pm_domain genpd;
|
||||
u8 pdr;
|
||||
unsigned int flags;
|
||||
char name[];
|
||||
};
|
||||
|
||||
static inline struct r8a779a0_sysc_pd *to_r8a779a0_pd(struct generic_pm_domain *d)
|
||||
{
|
||||
return container_of(d, struct r8a779a0_sysc_pd, genpd);
|
||||
}
|
||||
|
||||
static int r8a779a0_sysc_pd_power_off(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct r8a779a0_sysc_pd *pd = to_r8a779a0_pd(genpd);
|
||||
|
||||
pr_debug("%s: %s\n", __func__, genpd->name);
|
||||
return r8a779a0_sysc_power(pd->pdr, false);
|
||||
}
|
||||
|
||||
static int r8a779a0_sysc_pd_power_on(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct r8a779a0_sysc_pd *pd = to_r8a779a0_pd(genpd);
|
||||
|
||||
pr_debug("%s: %s\n", __func__, genpd->name);
|
||||
return r8a779a0_sysc_power(pd->pdr, true);
|
||||
}
|
||||
|
||||
static int __init r8a779a0_sysc_pd_setup(struct r8a779a0_sysc_pd *pd)
|
||||
{
|
||||
struct generic_pm_domain *genpd = &pd->genpd;
|
||||
const char *name = pd->genpd.name;
|
||||
int error;
|
||||
|
||||
if (pd->flags & PD_CPU) {
|
||||
/*
|
||||
* This domain contains a CPU core and therefore it should
|
||||
* only be turned off if the CPU is not in use.
|
||||
*/
|
||||
pr_debug("PM domain %s contains %s\n", name, "CPU");
|
||||
genpd->flags |= GENPD_FLAG_ALWAYS_ON;
|
||||
} else if (pd->flags & PD_SCU) {
|
||||
/*
|
||||
* This domain contains an SCU and cache-controller, and
|
||||
* therefore it should only be turned off if the CPU cores are
|
||||
* not in use.
|
||||
*/
|
||||
pr_debug("PM domain %s contains %s\n", name, "SCU");
|
||||
genpd->flags |= GENPD_FLAG_ALWAYS_ON;
|
||||
} else if (pd->flags & PD_NO_CR) {
|
||||
/*
|
||||
* This domain cannot be turned off.
|
||||
*/
|
||||
genpd->flags |= GENPD_FLAG_ALWAYS_ON;
|
||||
}
|
||||
|
||||
if (!(pd->flags & (PD_CPU | PD_SCU))) {
|
||||
/* Enable Clock Domain for I/O devices */
|
||||
genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
|
||||
genpd->attach_dev = cpg_mssr_attach_dev;
|
||||
genpd->detach_dev = cpg_mssr_detach_dev;
|
||||
}
|
||||
|
||||
genpd->power_off = r8a779a0_sysc_pd_power_off;
|
||||
genpd->power_on = r8a779a0_sysc_pd_power_on;
|
||||
|
||||
if (pd->flags & (PD_CPU | PD_NO_CR)) {
|
||||
/* Skip CPUs (handled by SMP code) and areas without control */
|
||||
pr_debug("%s: Not touching %s\n", __func__, genpd->name);
|
||||
goto finalize;
|
||||
}
|
||||
|
||||
if (!r8a779a0_sysc_power_is_off(pd->pdr)) {
|
||||
pr_debug("%s: %s is already powered\n", __func__, genpd->name);
|
||||
goto finalize;
|
||||
}
|
||||
|
||||
r8a779a0_sysc_power(pd->pdr, true);
|
||||
|
||||
finalize:
|
||||
error = pm_genpd_init(genpd, &simple_qos_governor, false);
|
||||
if (error)
|
||||
pr_err("Failed to init PM domain %s: %d\n", name, error);
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
static const struct of_device_id r8a779a0_sysc_matches[] __initconst = {
|
||||
{ .compatible = "renesas,r8a779a0-sysc", .data = &r8a779a0_sysc_info },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
struct r8a779a0_pm_domains {
|
||||
struct genpd_onecell_data onecell_data;
|
||||
struct generic_pm_domain *domains[R8A779A0_PD_ALWAYS_ON + 1];
|
||||
};
|
||||
|
||||
static struct genpd_onecell_data *r8a779a0_sysc_onecell_data;
|
||||
|
||||
static int __init r8a779a0_sysc_pd_init(void)
|
||||
{
|
||||
const struct r8a779a0_sysc_info *info;
|
||||
const struct of_device_id *match;
|
||||
struct r8a779a0_pm_domains *domains;
|
||||
struct device_node *np;
|
||||
void __iomem *base;
|
||||
unsigned int i;
|
||||
int error;
|
||||
|
||||
np = of_find_matching_node_and_match(NULL, r8a779a0_sysc_matches, &match);
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
info = match->data;
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
if (!base) {
|
||||
pr_warn("%pOF: Cannot map regs\n", np);
|
||||
error = -ENOMEM;
|
||||
goto out_put;
|
||||
}
|
||||
|
||||
r8a779a0_sysc_base = base;
|
||||
|
||||
domains = kzalloc(sizeof(*domains), GFP_KERNEL);
|
||||
if (!domains) {
|
||||
error = -ENOMEM;
|
||||
goto out_put;
|
||||
}
|
||||
|
||||
domains->onecell_data.domains = domains->domains;
|
||||
domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
|
||||
r8a779a0_sysc_onecell_data = &domains->onecell_data;
|
||||
|
||||
for (i = 0; i < info->num_areas; i++) {
|
||||
const struct r8a779a0_sysc_area *area = &info->areas[i];
|
||||
struct r8a779a0_sysc_pd *pd;
|
||||
|
||||
if (!area->name) {
|
||||
/* Skip NULLified area */
|
||||
continue;
|
||||
}
|
||||
|
||||
pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
|
||||
if (!pd) {
|
||||
error = -ENOMEM;
|
||||
goto out_put;
|
||||
}
|
||||
|
||||
strcpy(pd->name, area->name);
|
||||
pd->genpd.name = pd->name;
|
||||
pd->pdr = area->pdr;
|
||||
pd->flags = area->flags;
|
||||
|
||||
error = r8a779a0_sysc_pd_setup(pd);
|
||||
if (error)
|
||||
goto out_put;
|
||||
|
||||
domains->domains[area->pdr] = &pd->genpd;
|
||||
|
||||
if (area->parent < 0)
|
||||
continue;
|
||||
|
||||
error = pm_genpd_add_subdomain(domains->domains[area->parent],
|
||||
&pd->genpd);
|
||||
if (error) {
|
||||
pr_warn("Failed to add PM subdomain %s to parent %u\n",
|
||||
area->name, area->parent);
|
||||
goto out_put;
|
||||
}
|
||||
}
|
||||
|
||||
error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
|
||||
|
||||
out_put:
|
||||
of_node_put(np);
|
||||
return error;
|
||||
}
|
||||
early_initcall(r8a779a0_sysc_pd_init);
|
||||
|
|
@ -37,6 +37,10 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
|
|||
.modemr = 0x60,
|
||||
};
|
||||
|
||||
static const struct rst_config rcar_rst_r8a779a0 __initconst = {
|
||||
.modemr = 0x00, /* MODEMR0 and it has CPG related bits */
|
||||
};
|
||||
|
||||
static const struct of_device_id rcar_rst_matches[] __initconst = {
|
||||
/* RZ/G1 is handled like R-Car Gen2 */
|
||||
{ .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
|
||||
|
|
@ -67,6 +71,8 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
|
|||
{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
|
||||
{ .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 },
|
||||
{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
|
||||
/* R-Car V3U */
|
||||
{ .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_r8a779a0 },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -200,6 +200,11 @@ static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
|
|||
.id = 0x58,
|
||||
};
|
||||
|
||||
static const struct renesas_soc soc_rcar_v3u __initconst __maybe_unused = {
|
||||
.family = &fam_rcar_gen3,
|
||||
.id = 0x59,
|
||||
};
|
||||
|
||||
static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
|
||||
.family = &fam_shmobile,
|
||||
.id = 0x37,
|
||||
|
|
@ -291,6 +296,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
|
|||
#ifdef CONFIG_ARCH_R8A77995
|
||||
{ .compatible = "renesas,r8a77995", .data = &soc_rcar_d3 },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A779A0
|
||||
{ .compatible = "renesas,r8a779a0", .data = &soc_rcar_v3u },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_SH73A0
|
||||
{ .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
|
||||
#endif
|
||||
|
|
|
|||
55
include/dt-bindings/clock/r8a779a0-cpg-mssr.h
Normal file
55
include/dt-bindings/clock/r8a779a0-cpg-mssr.h
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a779A0 CPG Core Clocks */
|
||||
#define R8A779A0_CLK_Z0 0
|
||||
#define R8A779A0_CLK_ZX 1
|
||||
#define R8A779A0_CLK_Z1 2
|
||||
#define R8A779A0_CLK_ZR 3
|
||||
#define R8A779A0_CLK_ZS 4
|
||||
#define R8A779A0_CLK_ZT 5
|
||||
#define R8A779A0_CLK_ZTR 6
|
||||
#define R8A779A0_CLK_S1D1 7
|
||||
#define R8A779A0_CLK_S1D2 8
|
||||
#define R8A779A0_CLK_S1D4 9
|
||||
#define R8A779A0_CLK_S1D8 10
|
||||
#define R8A779A0_CLK_S1D12 11
|
||||
#define R8A779A0_CLK_S3D1 12
|
||||
#define R8A779A0_CLK_S3D2 13
|
||||
#define R8A779A0_CLK_S3D4 14
|
||||
#define R8A779A0_CLK_LB 15
|
||||
#define R8A779A0_CLK_CP 16
|
||||
#define R8A779A0_CLK_CL 17
|
||||
#define R8A779A0_CLK_CL16MCK 18
|
||||
#define R8A779A0_CLK_ZB30 19
|
||||
#define R8A779A0_CLK_ZB30D2 20
|
||||
#define R8A779A0_CLK_ZB30D4 21
|
||||
#define R8A779A0_CLK_ZB31 22
|
||||
#define R8A779A0_CLK_ZB31D2 23
|
||||
#define R8A779A0_CLK_ZB31D4 24
|
||||
#define R8A779A0_CLK_SD0H 25
|
||||
#define R8A779A0_CLK_SD0 26
|
||||
#define R8A779A0_CLK_RPC 27
|
||||
#define R8A779A0_CLK_RPCD2 28
|
||||
#define R8A779A0_CLK_MSO 29
|
||||
#define R8A779A0_CLK_CANFD 30
|
||||
#define R8A779A0_CLK_CSI0 31
|
||||
#define R8A779A0_CLK_FRAY 32
|
||||
#define R8A779A0_CLK_DSI 33
|
||||
#define R8A779A0_CLK_VIP 34
|
||||
#define R8A779A0_CLK_ADGH 35
|
||||
#define R8A779A0_CLK_CNNDSP 36
|
||||
#define R8A779A0_CLK_ICU 37
|
||||
#define R8A779A0_CLK_ICUD2 38
|
||||
#define R8A779A0_CLK_VCBUS 39
|
||||
#define R8A779A0_CLK_CBFUSA 40
|
||||
#define R8A779A0_CLK_R 41
|
||||
#define R8A779A0_CLK_OSC 42
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
|
||||
59
include/dt-bindings/power/r8a779a0-sysc.h
Normal file
59
include/dt-bindings/power/r8a779a0-sysc.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the Power Domain Register Numbers (PDR)
|
||||
*/
|
||||
|
||||
#define R8A779A0_PD_A1E0D0C0 0
|
||||
#define R8A779A0_PD_A1E0D0C1 1
|
||||
#define R8A779A0_PD_A1E0D1C0 2
|
||||
#define R8A779A0_PD_A1E0D1C1 3
|
||||
#define R8A779A0_PD_A1E1D0C0 4
|
||||
#define R8A779A0_PD_A1E1D0C1 5
|
||||
#define R8A779A0_PD_A1E1D1C0 6
|
||||
#define R8A779A0_PD_A1E1D1C1 7
|
||||
#define R8A779A0_PD_A2E0D0 16
|
||||
#define R8A779A0_PD_A2E0D1 17
|
||||
#define R8A779A0_PD_A2E1D0 18
|
||||
#define R8A779A0_PD_A2E1D1 19
|
||||
#define R8A779A0_PD_A3E0 20
|
||||
#define R8A779A0_PD_A3E1 21
|
||||
#define R8A779A0_PD_3DG_A 24
|
||||
#define R8A779A0_PD_3DG_B 25
|
||||
#define R8A779A0_PD_A1CNN2 32
|
||||
#define R8A779A0_PD_A1DSP0 33
|
||||
#define R8A779A0_PD_A2IMP01 34
|
||||
#define R8A779A0_PD_A2DP0 35
|
||||
#define R8A779A0_PD_A2CV0 36
|
||||
#define R8A779A0_PD_A2CV1 37
|
||||
#define R8A779A0_PD_A2CV4 38
|
||||
#define R8A779A0_PD_A2CV6 39
|
||||
#define R8A779A0_PD_A2CN2 40
|
||||
#define R8A779A0_PD_A1CNN0 41
|
||||
#define R8A779A0_PD_A2CN0 42
|
||||
#define R8A779A0_PD_A3IR 43
|
||||
#define R8A779A0_PD_A1CNN1 44
|
||||
#define R8A779A0_PD_A1DSP1 45
|
||||
#define R8A779A0_PD_A2IMP23 46
|
||||
#define R8A779A0_PD_A2DP1 47
|
||||
#define R8A779A0_PD_A2CV2 48
|
||||
#define R8A779A0_PD_A2CV3 49
|
||||
#define R8A779A0_PD_A2CV5 50
|
||||
#define R8A779A0_PD_A2CV7 51
|
||||
#define R8A779A0_PD_A2CN1 52
|
||||
#define R8A779A0_PD_A3VIP0 56
|
||||
#define R8A779A0_PD_A3VIP1 57
|
||||
#define R8A779A0_PD_A3VIP2 58
|
||||
#define R8A779A0_PD_A3VIP3 59
|
||||
#define R8A779A0_PD_A3ISP01 60
|
||||
#define R8A779A0_PD_A3ISP23 61
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A779A0_PD_ALWAYS_ON 64
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */
|
||||
Loading…
Reference in a new issue