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drm/bridge: tc358762: Guess the meaning of LCDCTRL bits

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The register content and behavior is very similar to TC358764 VP_CTRL.
All the bits except for unknown bit 6 also seem to match, even though
the datasheet is just not available. Add a comment and reuse the bit
definitions.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230615201902.566182-4-marex@denx.de
This commit is contained in:
Marek Vasut 2023-06-15 22:19:01 +02:00 committed by Robert Foss
parent 362fa8f6e6
commit 80382226ef
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GPG key ID: 3EFD900F76D1D784
1 changed files with 13 additions and 3 deletions
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16
drivers/gpu/drm/bridge/tc358762.c
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@ -41,8 +41,17 @@
#define DSI_LANEENABLE 0x0210 /* Enables each lane */
#define DSI_RX_START 1
/* LCDC/DPI Host Registers */
#define LCDCTRL 0x0420
/* LCDC/DPI Host Registers, based on guesswork that this matches TC358764 */
#define LCDCTRL 0x0420 /* Video Path Control */
#define LCDCTRL_MSF BIT(0) /* Magic square in RGB666 */
#define LCDCTRL_VTGEN BIT(4)/* Use chip clock for timing */
#define LCDCTRL_UNK6 BIT(6) /* Unknown */
#define LCDCTRL_EVTMODE BIT(5) /* Event mode */
#define LCDCTRL_RGB888 BIT(8) /* RGB888 mode */
#define LCDCTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */
#define LCDCTRL_DEPOL BIT(18) /* Polarity of DE signal */
#define LCDCTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */
#define LCDCTRL_VSDELAY(v) (((v) & 0xfff) << 20) /* VSYNC delay */
/* SPI Master Registers */
#define SPICMR 0x0450
@ -114,7 +123,8 @@ static int tc358762_init(struct tc358762 *ctx)
tc358762_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD);
tc358762_write(ctx, SPICMR, 0x00);
tc358762_write(ctx, LCDCTRL, 0x00100150);
tc358762_write(ctx, LCDCTRL, LCDCTRL_VSDELAY(1) | LCDCTRL_RGB888 |
LCDCTRL_UNK6 | LCDCTRL_VTGEN);
tc358762_write(ctx, SYSCTRL, 0x040f);
msleep(100);