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arm64: dts: imx8dxl: add usb1 and usb2 support
There are two chipidea usb controller in 8dxl. Add usb node at common connect subsystem. Enable two usb at imx8dxl_evk boards dts. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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3 changed files with 83 additions and 0 deletions
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@ -34,6 +34,35 @@ conn_ipg_clk: clock-conn-ipg {
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clock-output-names = "conn_ipg_clk";
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clock-output-names = "conn_ipg_clk";
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};
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};
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usbotg1: usb@5b0d0000 {
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compatible = "fsl,imx7ulp-usb";
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reg = <0x5b0d0000 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
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fsl,usbphy = <&usbphy1>;
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fsl,usbmisc = <&usbmisc1 0>;
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clocks = <&usb2_lpcg 0>;
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ahb-burst-config = <0x0>;
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tx-burst-size-dword = <0x10>;
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rx-burst-size-dword = <0x10>;
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power-domains = <&pd IMX_SC_R_USB_0>;
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status = "disabled";
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};
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usbmisc1: usbmisc@5b0d0200 {
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#index-cells = <1>;
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compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
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reg = <0x5b0d0200 0x200>;
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};
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usbphy1: usbphy@5b100000 {
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compatible = "fsl,imx7ulp-usbphy";
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reg = <0x5b100000 0x1000>;
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clocks = <&usb2_lpcg 1>;
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power-domains = <&pd IMX_SC_R_USB_0_PHY>;
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status = "disabled";
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};
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usdhc1: mmc@5b010000 {
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usdhc1: mmc@5b010000 {
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b010000 0x10000>;
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reg = <0x5b010000 0x10000>;
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@ -195,4 +224,14 @@ enet1_lpcg: clock-controller@5b240000 {
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"enet1_lpcg_ipg_s_clk";
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"enet1_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_ENET_1>;
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power-domains = <&pd IMX_SC_R_ENET_1>;
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};
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};
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usb2_lpcg: clock-controller@5b270000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b270000 0x10000>;
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#clock-cells = <1>;
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clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
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clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
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power-domains = <&pd IMX_SC_R_USB_0_PHY>;
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};
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};
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};
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@ -266,6 +266,40 @@ map0 {
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};
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};
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};
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};
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&usbphy1 {
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/* USB eye diagram tests result */
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fsl,tx-d-cal = <114>;
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status = "okay";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1>;
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srp-disable;
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hnp-disable;
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adp-disable;
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power-active-high;
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disable-over-current;
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status = "okay";
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};
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&usbphy2 {
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/* USB eye diagram tests result */
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fsl,tx-d-cal = <111>;
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status = "okay";
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};
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&usbotg2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg2>;
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srp-disable;
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hnp-disable;
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adp-disable;
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power-active-high;
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disable-over-current;
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status = "okay";
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};
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&usdhc1 {
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-0 = <&pinctrl_usdhc1>;
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@ -140,3 +140,13 @@ &usdhc3 {
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compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
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compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&usbotg1 {
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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/*
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* usbotg1 and usbotg2 share one clock
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* scfw disable clock access and keep it always on
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* in case other core (M4) use one of these.
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*/
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clocks = <&clk_dummy>;
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};
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