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clk: sunxi-ng: sun6i: Export video PLLs
The 2x outputs of the 2 video PLL clocks are directly used by the
HDMI controller block.
Export them so they can be referenced in the device tree.
Fixes: c6e6c96d8f
("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
parent
5da672cff0
commit
80815004a4
2 changed files with 10 additions and 2 deletions
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@ -27,7 +27,9 @@
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#define CLK_PLL_AUDIO_4X 4
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#define CLK_PLL_AUDIO_8X 5
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#define CLK_PLL_VIDEO0 6
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#define CLK_PLL_VIDEO0_2X 7
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/* The PLL_VIDEO0_2X clock is exported */
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#define CLK_PLL_VE 8
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#define CLK_PLL_DDR 9
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@ -35,7 +37,9 @@
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#define CLK_PLL_PERIPH_2X 11
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#define CLK_PLL_VIDEO1 12
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#define CLK_PLL_VIDEO1_2X 13
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/* The PLL_VIDEO1_2X clock is exported */
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#define CLK_PLL_GPU 14
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#define CLK_PLL_MIPI 15
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#define CLK_PLL9 16
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@ -43,8 +43,12 @@
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#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
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#define _DT_BINDINGS_CLK_SUN6I_A31_H_
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#define CLK_PLL_VIDEO0_2X 7
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#define CLK_PLL_PERIPH 10
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#define CLK_PLL_VIDEO1_2X 13
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#define CLK_CPU 18
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#define CLK_AHB1_MIPIDSI 23
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