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x86/amd-iommu: Export cache-coherency capability
This patch exports the capability of the AMD IOMMU to force cache coherency of DMA transactions through the IOMMU-API. This is required to disable some nasty hacks in KVM when this capability is not available. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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@ -2572,6 +2572,11 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
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static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
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unsigned long cap)
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{
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switch (cap) {
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case IOMMU_CAP_CACHE_COHERENCY:
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return 1;
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}
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return 0;
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}
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