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ARC: Make ARC bitops "safer" (add anti-optimization)
ARCompact/ARCv2 ISA provide that any instructions which deals with bitpos/count operand ASL, LSL, BSET, BCLR, BMSK .... will only consider lower 5 bits. i.e. auto-clamp the pos to 0-31. ARC Linux bitops exploited this fact by NOT explicitly masking out upper bits for @nr operand in general, saving a bunch of AND/BMSK instructions in generated code around bitops. While this micro-optimization has worked well over years it is NOT safe as shifting a number with a value, greater than native size is "undefined" per "C" spec. So as it turns outm EZChip ran into this eventually, in their massive muti-core SMP build with 64 cpus. There was a test_bit() inside a loop from 63 to 0 and gcc was weirdly optimizing away the first iteration (so it was really adhering to standard by implementing undefined behaviour vs. removing all the iterations which were phony i.e. (1 << [63..32]) | for i = 63 to 0 | X = ( 1 << i ) | if X == 0 | continue So fix the code to do the explicit masking at the expense of generating additional instructions. Fortunately, this can be mitigated to a large extent as gcc has SHIFT_COUNT_TRUNCATED which allows combiner to fold masking into shift operation itself. It is currently not enabled in ARC gcc backend, but could be done after a bit of testing. Fixes STAR 9000866918 ("unsafe "undefined behavior" code in kernel") Reported-by: Noam Camus <noamc@ezchip.com> Cc: <stable@vger.kernel.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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1 changed files with 9 additions and 26 deletions
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@ -50,8 +50,7 @@ static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
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* done for const @nr, but no code is generated due to gcc \
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* const prop. \
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*/ \
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if (__builtin_constant_p(nr)) \
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nr &= 0x1f; \
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nr &= 0x1f; \
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\
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__asm__ __volatile__( \
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"1: llock %0, [%1] \n" \
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@ -82,8 +81,7 @@ static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *
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\
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m += nr >> 5; \
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\
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if (__builtin_constant_p(nr)) \
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nr &= 0x1f; \
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nr &= 0x1f; \
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\
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/* \
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* Explicit full memory barrier needed before/after as \
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@ -129,16 +127,13 @@ static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
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unsigned long temp, flags; \
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m += nr >> 5; \
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\
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if (__builtin_constant_p(nr)) \
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nr &= 0x1f; \
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\
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/* \
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* spin lock/unlock provide the needed smp_mb() before/after \
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*/ \
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bitops_lock(flags); \
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\
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temp = *m; \
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*m = temp c_op (1UL << nr); \
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*m = temp c_op (1UL << (nr & 0x1f)); \
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\
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bitops_unlock(flags); \
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}
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@ -149,17 +144,14 @@ static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *
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unsigned long old, flags; \
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m += nr >> 5; \
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\
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if (__builtin_constant_p(nr)) \
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nr &= 0x1f; \
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\
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bitops_lock(flags); \
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\
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old = *m; \
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*m = old c_op (1 << nr); \
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*m = old c_op (1UL << (nr & 0x1f)); \
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\
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bitops_unlock(flags); \
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\
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return (old & (1 << nr)) != 0; \
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return (old & (1UL << (nr & 0x1f))) != 0; \
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}
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#endif /* CONFIG_ARC_HAS_LLSC */
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@ -174,11 +166,8 @@ static inline void __##op##_bit(unsigned long nr, volatile unsigned long *m) \
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unsigned long temp; \
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m += nr >> 5; \
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\
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if (__builtin_constant_p(nr)) \
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nr &= 0x1f; \
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\
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temp = *m; \
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*m = temp c_op (1UL << nr); \
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*m = temp c_op (1UL << (nr & 0x1f)); \
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}
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#define __TEST_N_BIT_OP(op, c_op, asm_op) \
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@ -187,13 +176,10 @@ static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long
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unsigned long old; \
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m += nr >> 5; \
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\
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if (__builtin_constant_p(nr)) \
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nr &= 0x1f; \
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\
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old = *m; \
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*m = old c_op (1 << nr); \
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*m = old c_op (1UL << (nr & 0x1f)); \
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\
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return (old & (1 << nr)) != 0; \
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return (old & (1UL << (nr & 0x1f))) != 0; \
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}
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#define BIT_OPS(op, c_op, asm_op) \
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@ -224,10 +210,7 @@ test_bit(unsigned int nr, const volatile unsigned long *addr)
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addr += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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mask = 1 << nr;
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mask = 1UL << (nr & 0x1f);
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return ((mask & *addr) != 0);
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}
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