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ASoC: correct s6000 I2S clock polarity
According to the data sheet data is clocked out on the falling edge and latched on the rising edge of the bit clock. While the left sample is transmitted the word clock line is low. Signed-off-by: Daniel Glöckner <dg@emlix.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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2 changed files with 3 additions and 3 deletions
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@ -252,10 +252,10 @@ static int s6000_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_IB_IF:
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case SND_SOC_DAIFMT_NB_NF:
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w |= S6_I2S_LEFT_FIRST;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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case SND_SOC_DAIFMT_NB_IF:
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w |= S6_I2S_RIGHT_FIRST;
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break;
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default:
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@ -43,7 +43,7 @@ static int s6105_hw_params(struct snd_pcm_substream *substream,
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/* set cpu DAI configuration */
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ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBM_CFM |
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SND_SOC_DAIFMT_IB_IF);
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SND_SOC_DAIFMT_NB_NF);
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if (ret < 0)
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return ret;
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