- Fixed error handling at probe time and uninitialized return code on

ep93xx (Arnd Bergman) - Fixed some kerneldoc warning on Cadence TTC (Randy Dunlap) - Fixed kerneldoc warning on Timer TI DM (Tony Lindgren) - Handle interrupt disabling when shutting down the timer on RISC-V timer (Joshua Yeong) - Add compatible string for the StarFive JH8100 clint (Sia Jee Heng) - Separate mtime and mtimecmp registers in DT bindings (Inochi Amaoto) -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEGn3N4YVz0WNVyHskqDIjiipP6E8FAmWTASUACgkQqDIjiipP 6E/eAwf+KEQXxEMk03d/sbehABXQ9TXB3KHZE4IgqQ9N+v4qxX5B9MsOHfvDv3La NQmrgVOcTSMzymhemy6TTXnKgQPqWy7QhqPF/+wTKqMxQAWeyPzYCVzo32CWLfrG el2uBtqhG7zq/0+9KEbw8ogSaV8+YqvJvHopTMe1hWXeRIr8rsaa5Hn3n3+caU68 YNcffng1F+15YJuceKmHFcT6yt1bFZJGqmxJYkrsiV8Wy8+SSObq71sLY+KlWkXX WnIKuU3snLHUW6yiL3ukRY92T9LIl73ditCvt+HHcVZUBTCS9ZZP7LAZ+euTxexJ 1aN5jdc82hb+KX6ZylNFHw54PKiXag== =5NMH -----END PGP SIGNATURE----- Merge tag 'timers-v6.8-rc1' of http://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clockevent/clocksource updates from Daniel Lezcano: - Fixed error handling at probe time and uninitialized return code on ep93xx (Arnd Bergman) - Fixed some kerneldoc warning on Cadence TTC (Randy Dunlap) - Fixed kerneldoc warning on Timer TI DM (Tony Lindgren) - Handle interrupt disabling when shutting down the timer on RISC-V timer (Joshua Yeong) - Add compatible string for the StarFive JH8100 clint (Sia Jee Heng) - Separate mtime and mtimecmp registers in DT bindings (Inochi Amaoto) Link: https://lore.kernel.org/lkml/0f07af92-e4b2-48de-88a6-dd9aa9e49743@linaro.org
2024-09-28 05:12:49 +00:00 · 2024-01-18 20:11:46 +01:00 · 2024-01-18 20:11:46 +01:00 · 80fe58cc17
commit 80fe58cc17
parent da65f29dad c0c4579d79
6 changed files with 36 additions and 12 deletions
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@ -33,6 +33,7 @@ properties:
              - sifive,fu540-c000-clint # SiFive FU540
              - starfive,jh7100-clint   # StarFive JH7100
              - starfive,jh7110-clint   # StarFive JH7110
+              - starfive,jh8100-clint   # StarFive JH8100
          - const: sifive,clint0        # SiFive CLINT v0 IP block
      - items:
          - enum:
--- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
+++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
@ -17,7 +17,12 @@ properties:
      - const: thead,c900-aclint-mtimer

  reg:
-    maxItems: 1
+    items:
+      - description: MTIMECMP Registers
+
+  reg-names:
+    items:
+      - const: mtimecmp

  interrupts-extended:
    minItems: 1
@ -28,6 +33,7 @@ additionalProperties: false
 required:
  - compatible
  - reg
+  - reg-names
  - interrupts-extended

 examples:
@ -39,5 +45,6 @@ examples:
                            <&cpu3intc 7>,
                            <&cpu4intc 7>;
      reg = <0xac000000 0x00010000>;
+      reg-names = "mtimecmp";
    };
 ...
--- a/drivers/clocksource/timer-cadence-ttc.c
+++ b/drivers/clocksource/timer-cadence-ttc.c
@ -69,7 +69,7 @@
 * @base_addr:	Base address of timer
 * @freq:	Timer input clock frequency
 * @clk:	Associated clock source
- * @clk_rate_change_nb	Notifier block for clock rate changes
+ * @clk_rate_change_nb:	Notifier block for clock rate changes
 */
 struct ttc_timer {
 	void __iomem *base_addr;
@ -134,7 +134,7 @@ static void ttc_set_interval(struct ttc_timer *timer,
 * @irq:	IRQ number of the Timer
 * @dev_id:	void pointer to the ttc_timer instance
 *
- * returns: Always IRQ_HANDLED - success
+ * Returns: Always IRQ_HANDLED - success
 **/
 static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
 {
@ -151,8 +151,9 @@ static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)

 /**
 * __ttc_clocksource_read - Reads the timer counter register
+ * @cs: &clocksource to read from
 *
- * returns: Current timer counter register value
+ * Returns: Current timer counter register value
 **/
 static u64 __ttc_clocksource_read(struct clocksource *cs)
 {
@ -173,7 +174,7 @@ static u64 notrace ttc_sched_clock_read(void)
 * @cycles:	Timer interval ticks
 * @evt:	Address of clock event instance
 *
- * returns: Always 0 - success
+ * Returns: Always %0 - success
 **/
 static int ttc_set_next_event(unsigned long cycles,
 					struct clock_event_device *evt)
@ -186,9 +187,12 @@ static int ttc_set_next_event(unsigned long cycles,
 }

 /**
- * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
- *
+ * ttc_shutdown - Sets the state of timer
 * @evt:	Address of clock event instance
+ *
+ * Used for shutdown or oneshot.
+ *
+ * Returns: Always %0 - success
 **/
 static int ttc_shutdown(struct clock_event_device *evt)
 {
@ -202,6 +206,12 @@ static int ttc_shutdown(struct clock_event_device *evt)
 	return 0;
 }

+/**
+ * ttc_set_periodic - Sets the state of timer
+ * @evt:	Address of clock event instance
+ *
+ * Returns: Always %0 - success
+ */
 static int ttc_set_periodic(struct clock_event_device *evt)
 {
 	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
--- a/drivers/clocksource/timer-ep93xx.c
+++ b/drivers/clocksource/timer-ep93xx.c
@ -155,9 +155,8 @@ static int __init ep93xx_timer_of_init(struct device_node *np)
 	ep93xx_tcu = tcu;

 	irq = irq_of_parse_and_map(np, 0);
-	if (irq == 0)
-		irq = -EINVAL;
-	if (irq < 0) {
+	if (!irq) {
+		ret = -EINVAL;
 		pr_err("EP93XX Timer Can't parse IRQ %d", irq);
 		goto out_free;
 	}
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@ -61,12 +61,19 @@ static int riscv_clock_next_event(unsigned long delta,
 	return 0;
 }

+static int riscv_clock_shutdown(struct clock_event_device *evt)
+{
+	riscv_clock_event_stop();
+	return 0;
+}
+
 static unsigned int riscv_clock_event_irq;
 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
 	.name			= "riscv_timer_clockevent",
 	.features		= CLOCK_EVT_FEAT_ONESHOT,
 	.rating			= 100,
 	.set_next_event		= riscv_clock_next_event,
+	.set_state_shutdown	= riscv_clock_shutdown,
 };

 /*
--- a/drivers/clocksource/timer-ti-dm.c
+++ b/drivers/clocksource/timer-ti-dm.c
@ -183,7 +183,7 @@ static inline u32 dmtimer_read(struct dmtimer *timer, u32 reg)
 * dmtimer_write - write timer registers in posted and non-posted mode
 * @timer:      timer pointer over which write operation is to perform
 * @reg:        lowest byte holds the register offset
- * @value:      data to write into the register
+ * @val:        data to write into the register
 *
 * The posted mode bit is encoded in reg. Note that in posted mode, the write
 * pending bit must be checked. Otherwise a write on a register which has a
@ -949,7 +949,7 @@ static int omap_dm_timer_set_int_enable(struct omap_dm_timer *cookie,

 /**
 * omap_dm_timer_set_int_disable - disable timer interrupts
- * @timer:	pointer to timer handle
+ * @cookie:	pointer to timer cookie
 * @mask:	bit mask of interrupts to be disabled
 *
 * Disables the specified timer interrupts for a timer.