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mtd: spi-nor: parse SFDP 4-byte Address Instruction Table
Add support for SFDP (JESD216B) 4-byte Address Instruction Table. This table is optional but when available, we parse it to get the 4-byte address op codes supported by the memory. Using these op codes is stateless as opposed to entering the 4-byte address mode or setting the Base Address Register (BAR). Flashes that have the 4BAIT table declared can now support SPINOR_OP_PP_1_1_4_4B and SPINOR_OP_PP_1_4_4_4B opcodes. Tested on MX25L25673G. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com> [tudor.ambarus@microchip.com: - rework erase and page program logic, - pass DMA-able buffer to spi_nor_read_sfdp(), - introduce SPI_NOR_HAS_4BAIT - various minor updates.] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
This commit is contained in:
parent
d05e21e3cf
commit
816873eaee
2 changed files with 193 additions and 1 deletions
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@ -121,6 +121,7 @@ struct sfdp_parameter_header {
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#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
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#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
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#define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */
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#define SFDP_SIGNATURE 0x50444653U
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#define SFDP_JESD216_MAJOR 1
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@ -3239,6 +3240,191 @@ static int spi_nor_parse_smpt(struct spi_nor *nor,
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return ret;
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}
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#define SFDP_4BAIT_DWORD_MAX 2
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struct sfdp_4bait {
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/* The hardware capability. */
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u32 hwcaps;
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/*
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* The <supported_bit> bit in DWORD1 of the 4BAIT tells us whether
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* the associated 4-byte address op code is supported.
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*/
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u32 supported_bit;
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};
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/**
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* spi_nor_parse_4bait() - parse the 4-Byte Address Instruction Table
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* @nor: pointer to a 'struct spi_nor'.
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* @param_header: pointer to the 'struct sfdp_parameter_header' describing
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* the 4-Byte Address Instruction Table length and version.
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* @params: pointer to the 'struct spi_nor_flash_parameter' to be.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_parse_4bait(struct spi_nor *nor,
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const struct sfdp_parameter_header *param_header,
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struct spi_nor_flash_parameter *params)
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{
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static const struct sfdp_4bait reads[] = {
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{ SNOR_HWCAPS_READ, BIT(0) },
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{ SNOR_HWCAPS_READ_FAST, BIT(1) },
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{ SNOR_HWCAPS_READ_1_1_2, BIT(2) },
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{ SNOR_HWCAPS_READ_1_2_2, BIT(3) },
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{ SNOR_HWCAPS_READ_1_1_4, BIT(4) },
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{ SNOR_HWCAPS_READ_1_4_4, BIT(5) },
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{ SNOR_HWCAPS_READ_1_1_1_DTR, BIT(13) },
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{ SNOR_HWCAPS_READ_1_2_2_DTR, BIT(14) },
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{ SNOR_HWCAPS_READ_1_4_4_DTR, BIT(15) },
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};
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static const struct sfdp_4bait programs[] = {
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{ SNOR_HWCAPS_PP, BIT(6) },
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{ SNOR_HWCAPS_PP_1_1_4, BIT(7) },
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{ SNOR_HWCAPS_PP_1_4_4, BIT(8) },
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};
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static const struct sfdp_4bait erases[SNOR_ERASE_TYPE_MAX] = {
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{ 0u /* not used */, BIT(9) },
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{ 0u /* not used */, BIT(10) },
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{ 0u /* not used */, BIT(11) },
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{ 0u /* not used */, BIT(12) },
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};
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struct spi_nor_pp_command *params_pp = params->page_programs;
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struct spi_nor_erase_map *map = &nor->erase_map;
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struct spi_nor_erase_type *erase_type = map->erase_type;
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u32 *dwords;
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size_t len;
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u32 addr, discard_hwcaps, read_hwcaps, pp_hwcaps, erase_mask;
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int i, ret;
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if (param_header->major != SFDP_JESD216_MAJOR ||
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param_header->length < SFDP_4BAIT_DWORD_MAX)
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return -EINVAL;
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/* Read the 4-byte Address Instruction Table. */
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len = sizeof(*dwords) * SFDP_4BAIT_DWORD_MAX;
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/* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
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dwords = kmalloc(len, GFP_KERNEL);
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if (!dwords)
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return -ENOMEM;
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addr = SFDP_PARAM_HEADER_PTP(param_header);
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ret = spi_nor_read_sfdp(nor, addr, len, dwords);
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if (ret)
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return ret;
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/* Fix endianness of the 4BAIT DWORDs. */
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for (i = 0; i < SFDP_4BAIT_DWORD_MAX; i++)
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dwords[i] = le32_to_cpu(dwords[i]);
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/*
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* Compute the subset of (Fast) Read commands for which the 4-byte
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* version is supported.
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*/
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discard_hwcaps = 0;
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read_hwcaps = 0;
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for (i = 0; i < ARRAY_SIZE(reads); i++) {
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const struct sfdp_4bait *read = &reads[i];
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discard_hwcaps |= read->hwcaps;
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if ((params->hwcaps.mask & read->hwcaps) &&
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(dwords[0] & read->supported_bit))
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read_hwcaps |= read->hwcaps;
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}
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/*
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* Compute the subset of Page Program commands for which the 4-byte
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* version is supported.
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*/
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pp_hwcaps = 0;
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for (i = 0; i < ARRAY_SIZE(programs); i++) {
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const struct sfdp_4bait *program = &programs[i];
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/*
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* The 4 Byte Address Instruction (Optional) Table is the only
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* SFDP table that indicates support for Page Program Commands.
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* Bypass the params->hwcaps.mask and consider 4BAIT the biggest
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* authority for specifying Page Program support.
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*/
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discard_hwcaps |= program->hwcaps;
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if (dwords[0] & program->supported_bit)
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pp_hwcaps |= program->hwcaps;
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}
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/*
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* Compute the subset of Sector Erase commands for which the 4-byte
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* version is supported.
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*/
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erase_mask = 0;
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for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
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const struct sfdp_4bait *erase = &erases[i];
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if (dwords[0] & erase->supported_bit)
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erase_mask |= BIT(i);
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}
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/* Replicate the sort done for the map's erase types in BFPT. */
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erase_mask = spi_nor_sort_erase_mask(map, erase_mask);
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/*
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* We need at least one 4-byte op code per read, program and erase
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* operation; the .read(), .write() and .erase() hooks share the
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* nor->addr_width value.
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*/
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if (!read_hwcaps || !pp_hwcaps || !erase_mask)
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goto out;
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/*
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* Discard all operations from the 4-byte instruction set which are
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* not supported by this memory.
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*/
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params->hwcaps.mask &= ~discard_hwcaps;
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params->hwcaps.mask |= (read_hwcaps | pp_hwcaps);
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/* Use the 4-byte address instruction set. */
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for (i = 0; i < SNOR_CMD_READ_MAX; i++) {
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struct spi_nor_read_command *read_cmd = ¶ms->reads[i];
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read_cmd->opcode = spi_nor_convert_3to4_read(read_cmd->opcode);
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}
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/* 4BAIT is the only SFDP table that indicates page program support. */
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if (pp_hwcaps & SNOR_HWCAPS_PP)
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spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP],
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SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
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if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_4)
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spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_1_4],
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SPINOR_OP_PP_1_1_4_4B,
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SNOR_PROTO_1_1_4);
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if (pp_hwcaps & SNOR_HWCAPS_PP_1_4_4)
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spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_4_4],
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SPINOR_OP_PP_1_4_4_4B,
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SNOR_PROTO_1_4_4);
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for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
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if (erase_mask & BIT(i))
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erase_type[i].opcode = (dwords[1] >>
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erase_type[i].idx * 8) & 0xFF;
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else
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spi_nor_set_erase_type(&erase_type[i], 0u, 0xFF);
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}
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/*
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* We set SNOR_F_HAS_4BAIT in order to skip spi_nor_set_4byte_opcodes()
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* later because we already did the conversion to 4byte opcodes. Also,
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* this latest function implements a legacy quirk for the erase size of
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* Spansion memory. However this quirk is no longer needed with new
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* SFDP compliant memories.
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*/
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nor->addr_width = 4;
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nor->flags |= SNOR_F_4B_OPCODES | SNOR_F_HAS_4BAIT;
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/* fall through */
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out:
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kfree(dwords);
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return ret;
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}
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/**
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* spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
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* @nor: pointer to a 'struct spi_nor'
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@ -3336,6 +3522,10 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
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err = spi_nor_parse_smpt(nor, param_header);
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break;
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case SFDP_4BAIT_ID:
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err = spi_nor_parse_4bait(nor, param_header, params);
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break;
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default:
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break;
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}
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@ -3925,7 +4115,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
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(JEDEC_MFR(info) == SNOR_MFR_SPANSION && mtd->size > SZ_16M))
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nor->flags |= SNOR_F_4B_OPCODES;
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if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES)
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if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
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!(nor->flags & SNOR_F_HAS_4BAIT))
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spi_nor_set_4byte_opcodes(nor);
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if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
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@ -234,6 +234,7 @@ enum spi_nor_option_flags {
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SNOR_F_USE_CLSR = BIT(5),
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SNOR_F_BROKEN_RESET = BIT(6),
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SNOR_F_4B_OPCODES = BIT(7),
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SNOR_F_HAS_4BAIT = BIT(8),
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};
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/**
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