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drm/amdgpu: Delete cgs wrapper functions for gpu memory manager
delete those cgs interfaces: amdgpu_cgs_alloc_gpu_mem amdgpu_cgs_free_gpu_mem amdgpu_cgs_gmap_gpu_mem amdgpu_cgs_gunmap_gpu_mem amdgpu_cgs_kmap_gpu_mem amdgpu_cgs_kunmap_gpu_mem Reviewed-by: Alex Deucher <alexdeucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ecc124b035
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2 changed files with 0 additions and 246 deletions
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@ -42,131 +42,6 @@ struct amdgpu_cgs_device {
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((struct amdgpu_cgs_device *)cgs_device)->adev
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static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
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enum cgs_gpu_mem_type type,
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uint64_t size, uint64_t align,
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cgs_handle_t *handle)
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{
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CGS_FUNC_ADEV;
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uint16_t flags = 0;
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int ret = 0;
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uint32_t domain = 0;
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struct amdgpu_bo *obj;
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/* fail if the alignment is not a power of 2 */
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if (((align != 1) && (align & (align - 1)))
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|| size == 0 || align == 0)
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return -EINVAL;
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switch(type) {
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case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
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case CGS_GPU_MEM_TYPE__VISIBLE_FB:
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flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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domain = AMDGPU_GEM_DOMAIN_VRAM;
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break;
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case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
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case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
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flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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domain = AMDGPU_GEM_DOMAIN_VRAM;
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break;
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case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
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domain = AMDGPU_GEM_DOMAIN_GTT;
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break;
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case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
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flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
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domain = AMDGPU_GEM_DOMAIN_GTT;
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break;
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default:
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return -EINVAL;
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}
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*handle = 0;
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ret = amdgpu_bo_create(adev, size, align, true, domain, flags,
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NULL, NULL, &obj);
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if (ret) {
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DRM_ERROR("(%d) bo create failed\n", ret);
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return ret;
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}
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*handle = (cgs_handle_t)obj;
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return ret;
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}
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static int amdgpu_cgs_free_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
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{
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struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
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if (obj) {
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int r = amdgpu_bo_reserve(obj, true);
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if (likely(r == 0)) {
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amdgpu_bo_kunmap(obj);
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amdgpu_bo_unpin(obj);
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amdgpu_bo_unreserve(obj);
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}
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amdgpu_bo_unref(&obj);
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}
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return 0;
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}
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static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
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uint64_t *mcaddr)
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{
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int r;
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struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
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WARN_ON_ONCE(obj->placement.num_placement > 1);
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r = amdgpu_bo_reserve(obj, true);
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if (unlikely(r != 0))
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return r;
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r = amdgpu_bo_pin(obj, obj->preferred_domains, mcaddr);
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amdgpu_bo_unreserve(obj);
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return r;
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}
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static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
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{
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int r;
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struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
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r = amdgpu_bo_reserve(obj, true);
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if (unlikely(r != 0))
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return r;
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r = amdgpu_bo_unpin(obj);
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amdgpu_bo_unreserve(obj);
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return r;
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}
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static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
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void **map)
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{
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int r;
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struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
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r = amdgpu_bo_reserve(obj, true);
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if (unlikely(r != 0))
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return r;
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r = amdgpu_bo_kmap(obj, map);
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amdgpu_bo_unreserve(obj);
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return r;
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}
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static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
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{
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int r;
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struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
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r = amdgpu_bo_reserve(obj, true);
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if (unlikely(r != 0))
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return r;
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amdgpu_bo_kunmap(obj);
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amdgpu_bo_unreserve(obj);
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return r;
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}
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static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
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{
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CGS_FUNC_ADEV;
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@ -906,12 +781,6 @@ static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool ena
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}
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static const struct cgs_ops amdgpu_cgs_ops = {
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.alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem,
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.free_gpu_mem = amdgpu_cgs_free_gpu_mem,
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.gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem,
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.gunmap_gpu_mem = amdgpu_cgs_gunmap_gpu_mem,
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.kmap_gpu_mem = amdgpu_cgs_kmap_gpu_mem,
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.kunmap_gpu_mem = amdgpu_cgs_kunmap_gpu_mem,
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.read_register = amdgpu_cgs_read_register,
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.write_register = amdgpu_cgs_write_register,
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.read_ind_register = amdgpu_cgs_read_ind_register,
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@ -28,18 +28,6 @@
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struct cgs_device;
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/**
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* enum cgs_gpu_mem_type - GPU memory types
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*/
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enum cgs_gpu_mem_type {
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CGS_GPU_MEM_TYPE__VISIBLE_FB,
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CGS_GPU_MEM_TYPE__INVISIBLE_FB,
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CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
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CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
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CGS_GPU_MEM_TYPE__GART_CACHEABLE,
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CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
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};
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/**
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* enum cgs_ind_reg - Indirect register spaces
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*/
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@ -130,89 +118,6 @@ struct cgs_display_info {
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typedef unsigned long cgs_handle_t;
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/**
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* cgs_alloc_gpu_mem() - Allocate GPU memory
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* @cgs_device: opaque device handle
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* @type: memory type
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* @size: size in bytes
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* @align: alignment in bytes
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* @handle: memory handle (output)
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*
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* The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
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* memory allocation. This guarantees that the MC address returned by
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* cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
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* FB memory types may be GART mapped depending on memory
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* fragmentation and memory allocator policies.
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*
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* If min/max_offset are non-0, the allocation will be forced to
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* reside between these offsets in its respective memory heap. The
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* base address that the offset relates to, depends on the memory
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* type.
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*
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* - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
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* - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address
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* - others: undefined, don't use with max_offset
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
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uint64_t size, uint64_t align,
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cgs_handle_t *handle);
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/**
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* cgs_free_gpu_mem() - Free GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
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/**
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* cgs_gmap_gpu_mem() - GPU-map GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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* @mcaddr: MC address (output)
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*
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* Ensures that a buffer is GPU accessible and returns its MC address.
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
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uint64_t *mcaddr);
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/**
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* cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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*
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* Allows the buffer to be migrated while it's not used by the GPU.
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
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/**
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* cgs_kmap_gpu_mem() - Kernel-map GPU memory
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*
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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* @map: Kernel virtual address the memory was mapped to (output)
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
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void **map);
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/**
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* cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
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/**
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* cgs_read_register() - Read an MMIO register
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* @cgs_device: opaque device handle
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@ -355,13 +260,6 @@ typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
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typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock);
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struct cgs_ops {
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/* memory management calls (similar to KFD interface) */
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cgs_alloc_gpu_mem_t alloc_gpu_mem;
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cgs_free_gpu_mem_t free_gpu_mem;
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cgs_gmap_gpu_mem_t gmap_gpu_mem;
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cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
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cgs_kmap_gpu_mem_t kmap_gpu_mem;
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cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
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/* MMIO access */
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cgs_read_register_t read_register;
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cgs_write_register_t write_register;
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@ -404,19 +302,6 @@ struct cgs_device
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#define CGS_OS_CALL(func,dev,...) \
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(((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
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#define cgs_alloc_gpu_mem(dev,type,size,align,handle) \
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CGS_CALL(alloc_gpu_mem,dev,type,size,align,handle)
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#define cgs_free_gpu_mem(dev,handle) \
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CGS_CALL(free_gpu_mem,dev,handle)
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#define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
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CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
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#define cgs_gunmap_gpu_mem(dev,handle) \
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CGS_CALL(gunmap_gpu_mem,dev,handle)
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#define cgs_kmap_gpu_mem(dev,handle,map) \
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CGS_CALL(kmap_gpu_mem,dev,handle,map)
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#define cgs_kunmap_gpu_mem(dev,handle) \
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CGS_CALL(kunmap_gpu_mem,dev,handle)
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#define cgs_read_register(dev,offset) \
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CGS_CALL(read_register,dev,offset)
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#define cgs_write_register(dev,offset,value) \
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