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pci-v4.10-fixes-1
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYgMnBAAoJEFmIoMA60/r8+PAQAKwSfmjn7y0cOabzrSOShrTA DutYzp1idgXlj8nmNIy04O/aQfK2GeXJlmWX3ye+D6c4Yn+m5CGpbCpx6WbWvvvX 9qgJmxGp5yq9iy5gi45iAyXp7kfBUvEbPd7pFRg3Rr3g73uGm3whd9ZcNUs7onBL B+p7q4Sq4/Hgy0yzbMkYe6s7ogXKa3lHt15WkETmaYaFayRlDIL1SAtFOddmi67r ooV4qm3QZm4JgCPxN0YHrA8ffUC1V9n9esPg11+UNUFxG9u5GZykQ8nedm+54HjT BVE7v9SqChf7lZArgTXM/d+L/mmK9Hmx6mfrgnZav+GiG8OZ27nzv/X7eabQ/bcu C/coO2BQhkGRcQ2yMa8JtQp2+BMPuc0io2i+U18TXAt+x7DzlW4nC1WOywb/Xuu3 aJhIEH8SFNnLoM5H+sXLWXsSYG86M4lKHw3ufzH/TOV85J301N/KH6OUdaYaEt+/ nta3xsz8qA+vDWmyYxpKzZGWQEqRDaBEJxd+bO+kSRcNfnFMUpQ9PkCLW19DVRWM YsLn81LYlLwH9z7pQ+y9okqZPViGs+Ta3fRLLeIlxDSJ6B2PAmoZdfa5LGKlrz6b nCT26YEPwK++nS3dGvh93k7FiTZE0LWJkfs734Wu9Jnz2C4wATqWwyCij5a2MXLn lilujaUV2xNhQPfZZ3Jk =4X8Q -----END PGP SIGNATURE----- Merge tag 'pci-v4.10-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: - recognize that a PCI-to-PCIe bridge originates a PCIe hierarchy, so we enumerate that hierarchy correctly - X-Gene: fix a change merged for v4.10 that broke MSI - Keystone: avoid reading undefined registers, which can cause asynchronous external aborts - Supermicro X8DTH-i/6/iF/6F: ignore broken _CRS that caused us to change (and break) existing I/O port assignments * tag 'pci-v4.10-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI/MSI: pci-xgene-msi: Fix CPU hotplug registration handling PCI: Enumerate switches below PCI-to-PCIe bridges x86/PCI: Ignore _CRS on Supermicro X8DTH-i/6/iF/6F PCI: designware: Check for iATU unroll only on platforms that use ATU
This commit is contained in:
commit
81aaeaac46
4 changed files with 23 additions and 11 deletions
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@ -114,6 +114,16 @@ static const struct dmi_system_id pci_crs_quirks[] __initconst = {
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DMI_MATCH(DMI_BIOS_VERSION, "6JET85WW (1.43 )"),
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},
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},
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/* https://bugzilla.kernel.org/show_bug.cgi?id=42606 */
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{
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.callback = set_nouse_crs,
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.ident = "Supermicro X8DTH",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
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DMI_MATCH(DMI_PRODUCT_NAME, "X8DTH-i/6/iF/6F"),
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DMI_MATCH(DMI_BIOS_VERSION, "2.0a"),
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},
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},
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/* https://bugzilla.kernel.org/show_bug.cgi?id=15362 */
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{
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@ -517,7 +517,7 @@ static int xgene_msi_probe(struct platform_device *pdev)
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rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/xgene:online",
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xgene_msi_hwirq_alloc, NULL);
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if (rc)
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if (rc < 0)
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goto err_cpuhp;
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pci_xgene_online = rc;
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rc = cpuhp_setup_state(CPUHP_PCI_XGENE_DEAD, "pci/xgene:dead", NULL,
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@ -807,11 +807,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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{
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u32 val;
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/* get iATU unroll support */
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pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
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dev_dbg(pp->dev, "iATU unroll: %s\n",
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pp->iatu_unroll_enabled ? "enabled" : "disabled");
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/* set the number of lanes */
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val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL);
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val &= ~PORT_LINK_MODE_MASK;
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@ -882,6 +877,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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* we should not program the ATU here.
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*/
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if (!pp->ops->rd_other_conf) {
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/* get iATU unroll support */
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pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
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dev_dbg(pp->dev, "iATU unroll: %s\n",
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pp->iatu_unroll_enabled ? "enabled" : "disabled");
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_MEM, pp->mem_base,
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pp->mem_bus_addr, pp->mem_size);
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@ -1169,6 +1169,7 @@ void set_pcie_port_type(struct pci_dev *pdev)
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pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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if (!pos)
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return;
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pdev->pcie_cap = pos;
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pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
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pdev->pcie_flags_reg = reg16;
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@ -1176,13 +1177,14 @@ void set_pcie_port_type(struct pci_dev *pdev)
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pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
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/*
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* A Root Port is always the upstream end of a Link. No PCIe
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* component has two Links. Two Links are connected by a Switch
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* that has a Port on each Link and internal logic to connect the
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* two Ports.
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* A Root Port or a PCI-to-PCIe bridge is always the upstream end
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* of a Link. No PCIe component has two Links. Two Links are
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* connected by a Switch that has a Port on each Link and internal
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* logic to connect the two Ports.
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*/
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type = pci_pcie_type(pdev);
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if (type == PCI_EXP_TYPE_ROOT_PORT)
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if (type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_PCIE_BRIDGE)
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pdev->has_secondary_link = 1;
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else if (type == PCI_EXP_TYPE_UPSTREAM ||
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type == PCI_EXP_TYPE_DOWNSTREAM) {
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