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staging: octeon-ethernet: spi: refactor spx block interrupt handling
Code for spx1 and spx0 block are identical, move it into a function. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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parent
124bcc5e74
commit
81f56d3320
1 changed files with 30 additions and 47 deletions
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@ -104,6 +104,32 @@ static void cvm_oct_stxx_int_pr(union cvmx_stxx_int_reg stx_int_reg, int index)
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index, 0);
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}
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static irqreturn_t cvm_oct_spi_spx_int(int index)
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{
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union cvmx_spxx_int_reg spx_int_reg;
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union cvmx_stxx_int_reg stx_int_reg;
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spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(index));
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cvmx_write_csr(CVMX_SPXX_INT_REG(index), spx_int_reg.u64);
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if (!need_retrain[index]) {
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spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(index));
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cvm_oct_spxx_int_pr(spx_int_reg, index);
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}
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stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(index));
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cvmx_write_csr(CVMX_STXX_INT_REG(index), stx_int_reg.u64);
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if (!need_retrain[index]) {
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stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(index));
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cvm_oct_stxx_int_pr(stx_int_reg, index);
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}
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cvmx_write_csr(CVMX_SPXX_INT_MSK(index), 0);
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cvmx_write_csr(CVMX_STXX_INT_MSK(index), 0);
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need_retrain[index] = 1;
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return IRQ_HANDLED;
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}
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static irqreturn_t cvm_oct_spi_rml_interrupt(int cpl, void *dev_id)
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{
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irqreturn_t return_status = IRQ_NONE;
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@ -111,54 +137,11 @@ static irqreturn_t cvm_oct_spi_rml_interrupt(int cpl, void *dev_id)
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/* Check and see if this interrupt was caused by the GMX block */
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rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS);
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if (rsl_int_blocks.s.spx1) { /* 19 - SPX1_INT_REG & STX1_INT_REG */
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if (rsl_int_blocks.s.spx1) /* 19 - SPX1_INT_REG & STX1_INT_REG */
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return_status = cvm_oct_spi_spx_int(1);
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union cvmx_spxx_int_reg spx_int_reg;
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union cvmx_stxx_int_reg stx_int_reg;
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spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(1));
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cvmx_write_csr(CVMX_SPXX_INT_REG(1), spx_int_reg.u64);
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if (!need_retrain[1]) {
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spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(1));
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cvm_oct_spxx_int_pr(spx_int_reg, 1);
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}
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stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(1));
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cvmx_write_csr(CVMX_STXX_INT_REG(1), stx_int_reg.u64);
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if (!need_retrain[1]) {
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stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(1));
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cvm_oct_stxx_int_pr(stx_int_reg, 1);
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}
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cvmx_write_csr(CVMX_SPXX_INT_MSK(1), 0);
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cvmx_write_csr(CVMX_STXX_INT_MSK(1), 0);
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need_retrain[1] = 1;
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return_status = IRQ_HANDLED;
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}
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if (rsl_int_blocks.s.spx0) { /* 18 - SPX0_INT_REG & STX0_INT_REG */
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union cvmx_spxx_int_reg spx_int_reg;
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union cvmx_stxx_int_reg stx_int_reg;
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spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(0));
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cvmx_write_csr(CVMX_SPXX_INT_REG(0), spx_int_reg.u64);
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if (!need_retrain[0]) {
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spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(0));
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cvm_oct_spxx_int_pr(spx_int_reg, 0);
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}
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stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(0));
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cvmx_write_csr(CVMX_STXX_INT_REG(0), stx_int_reg.u64);
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if (!need_retrain[0]) {
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stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(0));
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cvm_oct_stxx_int_pr(stx_int_reg, 0);
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}
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cvmx_write_csr(CVMX_SPXX_INT_MSK(0), 0);
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cvmx_write_csr(CVMX_STXX_INT_MSK(0), 0);
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need_retrain[0] = 1;
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return_status = IRQ_HANDLED;
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}
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if (rsl_int_blocks.s.spx0) /* 18 - SPX0_INT_REG & STX0_INT_REG */
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return_status = cvm_oct_spi_spx_int(0);
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return return_status;
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}
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