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[ARM] Adapt vic.c to allow for multiple VICs in a system.
Some SoCs have multiple VIC devices. Adapt the generic vic code to allow multiple implementations to be handled. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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3 changed files with 29 additions and 24 deletions
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@ -22,22 +22,21 @@
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#include <linux/list.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/vic.h>
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static void __iomem *vic_base;
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static void vic_mask_irq(unsigned int irq)
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{
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irq -= IRQ_VIC_START;
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writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR);
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void __iomem *base = get_irq_chipdata(irq);
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irq &= 31;
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writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
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}
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static void vic_unmask_irq(unsigned int irq)
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{
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irq -= IRQ_VIC_START;
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writel(1 << irq, vic_base + VIC_INT_ENABLE);
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void __iomem *base = get_irq_chipdata(irq);
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irq &= 31;
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writel(1 << irq, base + VIC_INT_ENABLE);
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}
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static struct irqchip vic_chip = {
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@ -46,43 +45,49 @@ static struct irqchip vic_chip = {
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.unmask = vic_unmask_irq,
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};
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void __init vic_init(void __iomem *base, u32 vic_sources)
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/**
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* vic_init - initialise a vectored interrupt controller
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* @base: iomem base address
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* @irq_start: starting interrupt number, must be muliple of 32
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* @vic_sources: bitmask of interrupt sources to allow
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*/
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void __init vic_init(void __iomem *base, unsigned int irq_start,
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u32 vic_sources)
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{
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unsigned int i;
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vic_base = base;
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/* Disable all interrupts initially. */
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writel(0, vic_base + VIC_INT_SELECT);
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writel(0, vic_base + VIC_INT_ENABLE);
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writel(~0, vic_base + VIC_INT_ENABLE_CLEAR);
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writel(0, vic_base + VIC_IRQ_STATUS);
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writel(0, vic_base + VIC_ITCR);
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writel(~0, vic_base + VIC_INT_SOFT_CLEAR);
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writel(0, base + VIC_INT_SELECT);
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writel(0, base + VIC_INT_ENABLE);
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writel(~0, base + VIC_INT_ENABLE_CLEAR);
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writel(0, base + VIC_IRQ_STATUS);
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writel(0, base + VIC_ITCR);
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writel(~0, base + VIC_INT_SOFT_CLEAR);
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/*
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* Make sure we clear all existing interrupts
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*/
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writel(0, vic_base + VIC_VECT_ADDR);
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writel(0, base + VIC_VECT_ADDR);
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for (i = 0; i < 19; i++) {
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unsigned int value;
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value = readl(vic_base + VIC_VECT_ADDR);
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writel(value, vic_base + VIC_VECT_ADDR);
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value = readl(base + VIC_VECT_ADDR);
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writel(value, base + VIC_VECT_ADDR);
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}
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for (i = 0; i < 16; i++) {
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void __iomem *reg = vic_base + VIC_VECT_CNTL0 + (i * 4);
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void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
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writel(VIC_VECT_CNTL_ENABLE | i, reg);
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}
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writel(32, vic_base + VIC_DEF_VECT_ADDR);
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writel(32, base + VIC_DEF_VECT_ADDR);
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for (i = 0; i < 32; i++) {
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unsigned int irq = IRQ_VIC_START + i;
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unsigned int irq = irq_start + i;
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set_irq_chip(irq, &vic_chip);
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set_irq_chipdata(irq, base);
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if (vic_sources & (1 << i)) {
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set_irq_handler(irq, do_level_IRQ);
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@ -112,7 +112,7 @@ void __init versatile_init_irq(void)
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{
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unsigned int i;
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vic_init(VA_VIC_BASE, ~(1 << 31));
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vic_init(VA_VIC_BASE, IRQ_VIC_START, ~(1 << 31));
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set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
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enable_irq(IRQ_VICSOURCE31);
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@ -39,7 +39,7 @@
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#define VIC_VECT_CNTL_ENABLE (1 << 5)
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#ifndef __ASSEMBLY__
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void vic_init(void __iomem *base, u32 vic_sources);
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void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);
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#endif
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#endif
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